Harshal Rawool

DevOps Engineer

Pune, Maharashtra, India8 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in Physical Design and Static Timing Analysis.
  • Proven track record in VLSI Design Engineering.
  • Strong educational background from prestigious institutions.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in semiconductor design and analysis.

Contact

LinkedIn

Skills

Core Skills

Physical DesignStatic Timing AnalysisLogic Synthesis

Other Skills

Circuit DesignDesign Engineering

Experience

8 yrs 9 mos
Total Experience
2 yrs 11 mos
Average Tenure
3 yrs 7 mos
Current Experience

Cadence design systems

Lead Engineer

Oct 2022 – Present · 3 yrs 7 mos · Pune, Maharashtra, India · Remote

Physical Design

Qualcomm

CAD Engineer (STA/ECO)

Sep 2021 – Sep 2022 · 1 yr · Bangalore Urban, Karnataka, India

Static Timing Analysis

Mediatek

VLSI Design Engineer

Jul 2017 – Sep 2021 · 4 yrs 2 mos · Bangalore

Logic Synthesis

Education

Indian Institute of Technology, Bombay

Master of Technology - MTech — Electrical Engineering (Microelectronics)

Jan 2014 – Jan 2017

University of Mumbai

Jan 2008 – Jan 2012

Smt. Indira Gandhi college of Engineering

Bachelor of Engineering (BE) — Instrumentation Technology

Jan 2008 – Jan 2012

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