vamsi krishna katragadda

DevOps Engineer

Hyderabad, Telangana, India7 yrs 3 mos experience
Highly Stable

Key Highlights

  • Expert in Place & Route flow for semiconductors.
  • Experience in 7nm and 6nm IP level synthesis.
  • Strong background in physical design engineering.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in physical design and implementation.

Contact

Skills

Other Skills

Static Timing AnalysisRTL to GDS IIMATLABUnixC (Programming Language)Clock Tree SynthesisPhysical DesignSynopsys toolsCadence EncounterRTL to GDSicc 2Synopsys PrimetimeMicrosoft Outlook

About

Physical Design Engineer with a good experience in designing and implementation in the semiconductors industry. Skilled in Place & Route flow of the physical design, Tcl-Tk, Cadence Encounter, Synopsys ICC & Primetime tools , and Perl. Have experience working on IP level synthesis & implementation and place & route implementation in lower nodes of 7nm and 6nm. Strong engineering professional with a Bachelor's degree focused in Electrical, Electronics and Communications Engineering from Gayatri Vidya Parishad College of Engineering (Autonomous), 530048(CC-13).

Experience

7 yrs 3 mos
Total Experience
2 yrs 10 mos
Average Tenure
1 yr 10 mos
Current Experience

Qualcomm

Senior Lead Engineer

Jul 2024Present · 1 yr 10 mos · Hyderabad, Telangana, India

Samsung semiconductor

2 roles

Associate Staff Engineer

Mar 2023Jul 2024 · 1 yr 4 mos · Bengaluru

Senior Engineer

Mar 2022Feb 2023 · 11 mos · Bengaluru

  • senior physical design engineer at Samsung Semiconductors India research

Soctronics

Physical Design Engineer

Jan 2019Mar 2022 · 3 yrs 2 mos · Hyderabad, Telangana, India

Amd

Contractor

Jan 2019Mar 2022 · 3 yrs 2 mos · Hyderabad, Telangana, India

Veda iit

ENGINEER TRAINEE

Jul 2018Jan 2019 · 6 mos · Hyderabad, Telangana, India

Education

Gayatri Vidya Parishad College of Engineering (Autonomous), 530048(CC-13)

Bachelor's degree

Jan 2014Jan 2018

Stackforce found 100+ more professionals with Static Timing Analysis & RTL to GDS II

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