Ankush Nehra

Software Engineer

Bengaluru, Karnataka, India7 yrs 10 mos experience
Highly Stable

Key Highlights

  • Expertise in SoC integration and RTL design.
  • Proven track record in high-quality chip delivery.
  • Strong experience with ARM protocols and signoffs.
Stackforce AI infers this person is a Semiconductor Engineer with expertise in SoC design and integration.

Contact

Skills

Core Skills

Rtl DesignSoc Integration

Other Skills

VerilogTCLReset ArchitectureScriptingRDCVery-Large-Scale Integration (VLSI)System on a Chip (SoC)Shell ScriptingCDCvim

About

SoC Integration Engineer with work experience of 3 years in the VLSI industry. I have worked on automotive SoCs and gain the knowledge of basics of reset architecture, clocking architecture, ARM protocols like AHB, APB, and signoffs like lint, LEC, CDC, and RDC to deliver quality chip top level RTL.

Experience

7 yrs 10 mos
Total Experience
3 yrs 6 mos
Average Tenure
10 mos
Current Experience

Meta

ASIC Design Engineer

Jul 2025Present · 10 mos · On-site

Google

ASIC RTL Design Engineer

Sep 2021Aug 2025 · 3 yrs 11 mos · India

  • Working on Google tensor SoC for upcoming pixel phones.
  • Complete ownership of ARM based DMA subsystem. Driving architecture discussion with arch team to implement in RTL.
  • All quality checks like lint, cdc, vclp, elab synth to ensure good quality of RTL.
  • Also worked on delivering the SoC level upf to DV and PD team.
RTL DesignVerilog

Nxp semiconductors

2 roles

Senior Design Engineer

Apr 2021Sep 2021 · 5 mos

TCLReset Architecture

Design Engineer

Jul 2018Apr 2021 · 2 yrs 9 mos

  • Working in SoC integration team and involved in the following tasks:
  • Reset integration to all the IPs in the SoC by taking care of reset synchronization and clock requirement during the reset.
  • Redesigned iomux cell to make it splitable, then blasted the iomux and iomux cells and automated the process to place all blocks in correct hierarchy to ease the timing and congestion in the backend.
  • Integrated motor control subsystem IPs like ADCs, PWM generation modules, and timers.
  • Generated iomux RTL from system specification and integrated at SoC level.
  • LEC signoff between blasted and flat design at SoC level.
  • RDC signoff at SoC level by plugging hierarchical data models of subsystems at the top level.
  • Scripting to develops and improve integration flows.

Education

Delhi Technological University

Bachelor of Technology (B.Tech.) — Electronics and Communications Engineering

Jan 2014Jan 2018

Shri daulat ram public sr. sec. school

High school — Non medical

Jan 2010Jan 2014

Stackforce found 100+ more professionals with Rtl Design & Soc Integration

Explore similar profiles based on matching skills and experience