Jothish Rajamohan

Software Engineer

Tirunelveli, Tamil Nadu, India6 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in IC Packaging and ASIC design.
  • Strong foundation in Universal Verification Methodology.
  • Proven internship experience at leading tech companies.
Stackforce AI infers this person is a semiconductor design engineer with expertise in IC packaging and verification methodologies.

Contact

LinkedIn

Skills

Core Skills

Ic PackagingApplication-specific Integrated Circuits (asic)

Other Skills

EngineeringUniversal Verification Methodology (UVM)SystemVerilog

Experience

6 yrs 9 mos
Total Experience
3 yrs 4 mos
Average Tenure
3 yrs 11 mos
Current Experience

Intel corporation

2 roles

IC Package Design Engineer

Jun 2022 – Present · 3 yrs 11 mos

IC PackagingEngineeringUniversal Verification Methodology (UVM)SystemVerilogApplication-Specific Integrated Circuits (ASIC)

Graduate Technical Intern

Aug 2021 – May 2022 · 9 mos

Juniper networks

Intern 3 ASIC Engineering

Jan 2020 – Jun 2020 · 5 mos · Bengaluru, Karnataka, India

National cadet corps - india

Cadet

Jun 2016 – Apr 2019 · 2 yrs 10 mos · Tamil Nadu, India

  • Completed C certificate with 'A' Grade

Education

Vellore Institute of Technology

Master of Technology - MTech — VLSI Design

Jan 2020 – Jan 2022

PSG College of Technology

Bachelor of Engineering - BE

Jan 2016 – Jan 2020

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