S

SACHIN P.

Software Engineer

Bengaluru, Karnataka, India13 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expertise in VLSI design verification.
  • Proficient in UVM and SystemVerilog.
  • Strong background in semiconductor engineering.
Stackforce AI infers this person is a VLSI Design Verification Engineer with expertise in semiconductor technologies.

Contact

LinkedIn

Skills

Core Skills

Semiconductor EngineeringDigital Designs

Other Skills

DesignElectronic CircuitsUVMSOC verificationVerilogElectronicsResearchAssembly LanguageC++C (Programming Language)PythonSystem VerilogEtherNet/IPFunctional VerificationMemory Controllers

About

Experienced Design Verification Engineer with a demonstrated history of working in the VLSI industry. Skilled in Universal Verification Methodology (UVM), SystemVerilog Language. Strong engineering professional graduated from HCET/RGPV.

Experience

13 yrs 3 mos
Total Experience
3 yrs 3 mos
Average Tenure
6 yrs 5 mos
Current Experience

Qualcomm

2 roles

Senior Lead Engineer

Dec 2022 – Present · 3 yrs 5 mos

Semiconductor EngineeringDesign

Senior Engineer

Dec 2019 – Dec 2022 · 3 yrs

Digital DesignsElectronic Circuits

Wipro

Design Verification Engineer

Sep 2018 – Nov 2019 · 1 yr 2 mos · Bangalore

Tessolve

Design Verification Engineer

Jul 2016 – Aug 2018 · 2 yrs 1 mo · Bangalore

Hcet/rgpv

Student

Jun 2011 – Jan 2015 · 3 yrs 7 mos

Education

Birla Institute of Technology and Science, Pilani

Master of Technology - MTech — Microelectronics

Jun 2021 – Dec 2023

HCET/RGPV

Jan 2011 – Jan 2015

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