Payavula Swathi

Software Engineer

Bengaluru, Karnataka, India5 yrs 7 mos experience

Key Highlights

Expert in RTL design and verification methodologies.
Hands-on experience with leading EDA tools.
Strong foundation in VLSI systems and digital design.

Stackforce AI infers this person is a Semiconductor Engineer with expertise in RTL design and verification.

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Skills

Core Skills

Very-large-scale Integration (vlsi)Rtl DesignSystemverilog

Other Skills

Functional TestingPythonVerilog HDLAdvanced Digital DesignRISC-V ISA & RV32I RTL DESIGNSystem Verilog for VerificationUniversal Verification MethodologyUniversal Verification Methodology (UVM)Digital Circuit DesignVerilogCUnit TestingDebuggingIntegration TestingEmbedded Software

Experience

5 yrs 7 mos

Total Experience

1 yr 10 mos

Average Tenure

1 yr 10 mos

Current Experience

Nvidia

Senior ASIC Engineer

Jul 2024 – Present · 1 yr 10 mos · India

Very-Large-Scale Integration (VLSI)Functional TestingPythonVerilog HDLAdvanced Digital DesignRISC-V ISA & RV32I RTL DESIGN+21

Synopsys inc

ASIC Digital Design Engr II

Jul 2022 – Jul 2024 · 2 yrs · Bengaluru, Karnataka, India

Worked in USB IP RTL Design. Worked on RTL design, Simulation, CDC , RDC, linting, Static Timing Analysis, Synthesis and documentation
Hands-on experience on Synopsys tools like VCS, Verdi, Spyglass, VC Spyglass, Design Compiler, VC Formal
Have good knowledge on Verilog, System Verilog, python and Tcl scripting

RTL DesignSystemVerilogUSB IP RTL DesignSimulationCDCRDC+8

National institute of technology, tiruchirappalli

Teaching Assistant

Jan 2021 – May 2022 · 1 yr 4 mos · Tiruchirappalli, Tamil Nadu, India

Worked as a Teaching Assistant during my M.Tech at NIT Tiruchirapalli.
Collaborated in dealing with subjects including Digital Electronics and Analog Integrated Circuits.
Managed Digital Electronics lab, AIC Lab, Microprocessor lab as Laboratory Assistant

Cadence VirtuosoLTSpice