Prashanth Vallur

Director of Engineering

Bengaluru, Karnataka, India25 yrs 5 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 20+ years of VLSI industry experience
  • Proven track record in team management
  • Strong focus on innovation and productivity
Stackforce AI infers this person is a leader in VLSI design and engineering management.

Contact

Skills

Core Skills

Ip Design LeadershipTeam ManagementHigh-speed Ip DesignMixed-signal Circuit DesignDigital DesignSerdes ImplementationDigital And Mixed-signal Ip Design

Other Skills

Integrated Circuit DesignProject ManagementVLSIPower ManagementAnalog Circuit DesignMixed SignalLow-power DesignDigital Circuit DesignLogic DesignPhysical DesignHigh-speed Digital DesignDigital SystemsResearchStatic Timing AnalysisPrimetime

About

- 20+ years of VLSI industry experience with expertise in IP design leadership - 15+ years of experience in managing design teams in analog, digital, mixed-signal IP design - End-to-end ownership spanning across definition, architecture, design, silicon char and productization - Direct experience in wide variety of IP including high-speed PHYs, clock IP, power management, sensors, IO interface, etc. - Strong knowledge base in all functions of IP design including Circuit, RTL, DV, Physical design, Layout, DFT, etc. - Constant growth in size, scope and efficiency of teams managed - Solid track record of managing multiple large teams in parallel with very low attrition - Key traits include strong domain knowledge, high ownership/accountability and constant focus on Innovation - Proven track record of building strong technical teams with diverse set of individuals and skills - Mentored many engineers into key technical leadership roles - Drove various productivity and methodology improvement initiatives with proven results - Very strong communication and presentation skills - Consistent desire to learn and adapt self and others - Always led by example, inspiring teams to deliver their best

Experience

25 yrs 5 mos
Total Experience
8 yrs 5 mos
Average Tenure
16 yrs 9 mos
Current Experience

Amd

4 roles

Senior Director, Design Engineering

Promoted

Jan 2023Present · 3 yrs 4 mos

  • Managing multiple large design teams responsible for a wide variety of IP that cater to all products at AMD
Integrated Circuit DesignProject ManagementVLSIPower ManagementIP Design LeadershipTeam Management

Engineering Fellow

Promoted

Jul 2019Dec 2022 · 3 yrs 5 mos

MTS, SMTS & PMTS Design Engineer

Jun 2010Jun 2019 · 9 yrs

  • Responsible for the design of various high-speed low-power analog mixed-signal circuits/IP in AMD's Microprocessor products across various technology nodes.
Analog Circuit DesignMixed SignalLow-power DesignHigh-speed IP DesignMixed-signal Circuit Design

MTS Design Engineer

Jun 2009Jun 2010 · 1 yr

  • Digital Design & Implementation in SERDES team, worked on high speed designs in PCIe/HT-PHY IP
Digital Circuit DesignLogic DesignPhysical DesignDigital DesignSERDES Implementation

Texas instruments

Senior High Speed Digital Design Engineer

Jan 2003May 2009 · 6 yrs 4 mos · Dallas-Fort Worth Metroplex

  • Design of High-speed digital and mixed-signal IP
High-speed Digital DesignMixed SignalDigital and Mixed-signal IP Design

University of texas at dallas

Research Assistant

Aug 2000Dec 2002 · 2 yrs 4 mos · Dallas-Fort Worth Metroplex

  • Worked as Research Assistant and Teaching Assistant while pursuing Masters in Electrical Engineering in Digital Systems track. Did thesis on "High-Speed Pipelined Arithmetic Circuits" under Dr. Poras Balsara.
Digital SystemsResearch

Education

The University of Texas at Dallas

MS — Electrical Engineering

Jan 2000Jan 2002

Sri Venkateswara University

B.S — Electronics and Communications Engineering

Jan 1996Jan 2000

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