Shailesh Talele

CEO

Bengaluru, Karnataka, India20 yrs 9 mos experience

Highly Stable

Key Highlights

Led a team of 12-18 engineers at Qualcomm.
Expertise in VLSI engineering with Intel and Qualcomm.
Experience in both pre-silicon and post-silicon validation.

Stackforce AI infers this person is a VLSI Engineering expert with extensive experience in ASIC and CPU design.

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Skills

Core Skills

Design ImplementationCpu IntegrationIp ArchitectureTiming SignoffCustom Circuit DesignMixed Signal Ip Design

Other Skills

Logic SynthesisCoverage AnalysisElectrical EngineeringCoaching & MentoringPresentation SkillsUnified Power Format (UPF)Design ReviewHardware EngineeringProblem SolvingEngineering ManagementMultiple SitesAnalytical SkillsDesign EngineeringCommunicationPhysical Design

About

After my Masters in Microelectronics from BITS Pilani, I worked at Intel in the MSIP team. As part of the design & signoff charter, I have experience of component & circuit design and characterization, IP design, pre-silicon verification, post-silicon validation and STA signoff. Working on variety of serial IOs across teams, sites and clients for IP & FC timing signoff was a great learning experience. To broaden my skillset into ASIC joined Qualcomm CPU team to implement cores with best PPA optimization. Here I gained exposure to synthesis, constraint verification, LEC, CLP, ECO implementation, custom timing checks and HSTA signoff methodologies. Working on a mix of latest EDA tools, tech nodes and timelines second to none in the industry is an overwhelming execution experience. Managing a team of around 12-18 talented and hardworking engineers delivering over 4-5 programs yearly has been a great experience as well. Overall, a great experience at both Intel and Qualcomm! Thanks to all my past and present colleagues, managers and staff, with whom I have explored the world of VLSI engineering!

Experience

20 yrs 9 mos

Total Experience

10 yrs 10 mos

Average Tenure

9 yrs 10 mos

Current Experience

Qualcomm

2 roles

SOC Chip Lead

Apr 2024 – Present · 2 yrs 1 mo

CPU Implementation Team Lead

Jul 2016 – Apr 2024 · 7 yrs 9 mos

Leading and grooming a team of dedicated engineers on implementation and integration of ARM CPU subsystem into wireless SOCs. The roles and responsibilities primarily involve Design implementation - Logical & Physical Synthesis, LEC, CLP, Constraints and sign-off of leading-edge CPU implementation.

Logic SynthesisCoverage AnalysisDesign ImplementationCPU Integration

Intel corporation

2 roles

Digital Design Engineer / STA Lead

May 2010 – Jun 2016 · 6 yrs 1 mo · Bangalore, India

IP Architecture driven clock definitions, timing budgets, Constraints Coding, design partitioning, block/cell characterization, methodology & signoff checks development, CTS exceptions, Noise analysis, ETM quality checks, SDF generation, timing DRC closure, sub-block signoff and integration in hierarchical model, Hard IP Signoff

Coverage AnalysisElectrical EngineeringIP ArchitectureTiming Signoff

Component Design Engineer

Jul 2005 – Apr 2010 · 4 yrs 9 mos · Bangalore, India

Custom Circuit Design, Mixed Signal IP design & characterization, IP Delivery Execution & Customer Documentation Review, Circuit and Architecture Specs documentation, Pre & Post Silicon Validation, FV & Fast Spice Sims based design verification, RV, Aging analysis for reliability, Silicon & Board/Platform Level Debug, Timing Signoff of Analog design through spice sims based dynamic timing analysis using Ocean scripts, LIB model generation at cell & IP level.

Coverage AnalysisElectrical EngineeringCustom Circuit DesignMixed Signal IP Design