Munish Jassi

CTO

Germany11 yrs 2 mos experience

Highly Stable

Key Highlights

Expert in SoC architecture for automotive applications.
Published multiple papers on EDA tools and methodologies.
Led teams in developing advanced ADAS solutions.

Stackforce AI infers this person is a highly skilled automotive SoC architect with expertise in embedded systems and ADAS technologies.

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Skills

Core Skills

SocHw/sw IntegrationAdasEmbedded Systems

Other Skills

SoC architectureHW/SW partitioningfunctional safetyCompute clustersMotion estimation HW IPsADAS perception algorithmsNPU IP architectureSoC design space explorationDigital Systems synthesisFPGAVHDLSystemCStatic Timing AnalysisVerilogXilinx

About

Publications TODAES'18, M. Jassi et al., Graph-Grammar-Based IP-Integration (GRIP) - An EDA Tool for Software-Defined SoCs GLSVLSI’16, M. Jassi et al., Hardware-Accelerated Software Libraries Drivers Generation for IP-Centric SoC Designs DATE’16, M. Jassi et al., GRIP: Graph-Rewriting-Based IP-Integration - An EDA Tool for SW Defined SoC Design SMACD’15, M. Jassi et al., Automation of FPGA Performance Monitoring and Debugging Using IP-XACT and Graph-Grammars DAC’15, M. Jassi et al., GRIP: Grammar-Based IP Integration and Packaging for Acceleration-Rich SoC Designs

Experience

11 yrs 2 mos

Total Experience

2 yrs 10 mos

Average Tenure

Current Experience

Samsung electronics

HW SoC Expert/SoC Architect

Jun 2019 – Sep 2020 · 1 yr 3 mos · Munich

Responsible for Exynos Auto ADAS SoC architecture
SoC technical concepts development - Compute clusters (CPU/NPU/DSP/GPU), HW/SW partitioning, human/machine vision ISP pipeline, Memories hierarchy, scalable multiple SoC architectures, functional safety (ASIL B/D)
Product alignment with key stakeholders. Leading automotive RFQ response teams

SoC architectureHW/SW partitioningfunctional safetyCompute clustersSoCHW/SW integration

Nxp semiconductors

Systems Architect - ADAS

Jun 2017 – May 2019 · 1 yr 11 mos · Munich, Bavaria, Germany

Our team is responsible for S32Vx Vision SoC products and customers requirements management.
Responsible for Motion estimation HW IPs (DOF, SOF), NPU IP - architecture, data flow, SW frameworks and benchmarks
ADAS perception algorithms/DNNs for front-view camera and SVM applications.

Motion estimation HW IPsADAS perception algorithmsNPU IP architectureADASSoC

Technical university of munich

Wissenschaftlicher Mitarbeiter

Jan 2012 – Jan 2017 · 5 yrs · Munich Area, Germany

Doctoral Thesis: SoC design space exploration methodologies for hardware accelerators-rich designs for machine vision
Developed and lectured a new M.Sc. course: Synthesis of Digital Systems [2013-2017].

SoC design space explorationDigital Systems synthesisSoCEmbedded Systems