Prashanth Jadhav

Director of Engineering

Bengaluru, Karnataka, India14 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

Stackforce AI infers this person is a semiconductor design engineer with expertise in VLSI and ASIC technologies.

VlsiAsicDebuggingValidation

CVerilogVHDLSoCModelSimC++MatlabSystemVerilogPerlSemiconductorsEDAEmbedded SystemsICCoverage analysis

14 yrs

Total Experience

2 yrs 9 mos

Average Tenure

5 yrs

Current Experience

3 roles

Promoted

Jul 2023 – Present · 2 yrs 10 mos

VLSICVerilogASICVHDLSoC+10

Apr 2022 – Jul 2023 · 1 yr 3 mos

Apr 2021 – Mar 2022 · 11 mos

Jan 2019 – Apr 2021 · 2 yrs 3 mos

Dec 2016 – Jan 2019 · 2 yrs 1 mo

Feb 2016 – Dec 2016 · 10 mos · Bangalore

3 roles

Jan 2016 – Feb 2016 · 1 mo · Bangalore

Validating the pattern generation flow which is currently implemented.
DCSU based AC Scan testing.
Broken Scan chain debug and giving feedback to implementation group.
Coverage analysis .
Validation of generated patterns for both transition and stuck-at faults (5 Mhz and at-speed frequency).
Mapping of all generated patterns to the TOP and validating patterns from CHIP level.
RAM BIST pattern generation and validation.
Simulation failure debug for Scan patterns and RAMBIST patterns.
Top Level hook-up check using Cadence Encounter Test.
Parallel Instance Verification of multiple instantiated blocks.

Jul 2012 – Dec 2015 · 3 yrs 5 mos · Bangalore

Validating the pattern generation flow which is currently implemented.
DCSU based AC Scan testing.
Broken Scan chain debug and giving feedback to implementation group.
Coverage analysis .
Validation of generated patterns for both transition and stuck-at faults (5 Mhz and at-speed frequency).
Mapping of all generated patterns to the TOP and validating patterns from CHIP level.
RAM BIST pattern generation and validation.
Simulation failure debug for Scan patterns and RAMBIST patterns.
Top Level hook-up check using Cadence Encounter Test.
Parallel Instance Verification of multiple instantiated blocks.