Bhawna Tomar

Program Manager

Bengaluru, Karnataka, India21 yrs 6 mos experience
Highly Stable

Key Highlights

  • Expert in VLSI design and management.
  • Proven track record in leading cross-functional teams.
  • Holder of five patents in semiconductor technologies.
Stackforce AI infers this person is a Semiconductor Engineering expert with extensive experience in VLSI design and program management.

Contact

Skills

Core Skills

Program ManagementSemiconductorsIp DevelopmentHardware EngineeringMemory DesignSoc DesignPost-silicon ValidationTeam LeadershipAnalog DesignClock DistributionDram DesignCustom Circuit Design

Other Skills

Business StrategyEnterprise Risk ManagementGovernance, Risk Management, and Compliance (GRC)Integrated Circuits (IC)LeadershipOperational ExcellenceStrategic PlanningSystem on a Chip (SoC)Component DesignIP SolutionsPower DistributionProblem SolvingDesign DevelopmentProcess AlignmentPresentation Skills

About

VLSI Professional with in depth understanding of design cycle from Architecture to Circuit design, Layout, RTL to GDS design for Tapeout and beyond. Handling multiple parallel projects for program scope involving complete ownership from design to qualification. Fast-PGMP certified Technical program manager and Certified Peoples Manager Program for employee motivation, goal setting and making them high performing team for organization growth. Involved in meticulous planning and reviews of Turnkey projects involving complete design to Tapeout for SOC delivery and Chiplets that cater to multiple design integration and verification of multi chip environment. Special expertise in managing designs with Agile practices and water fall as per project requirements. In depth knowledge for Custom Circuit Designer for state of art Memory (SRAM, DRAM and Flash) technologies.Experienced in working on Memory Architecture Datapath, Data Synchronizarion, DLL design. DRAM-DDR, Nand Flash-TM IO design and ESD design. Holding five patents and few publications with strong problem solving capabilities. Spear headed task forces for resolving the several design challenges faced in course of projects and brought value addition, innovation amidst tight budget and schedule constraints, Drove multiple teams and facilitated resolution of cross-functional design and delivery issues and ran CCB approval forums for control on quality, cost and ROI. Used influence and expertise to direct and delegate action to resolve issues and expedite the closure. Expert at change control and risk management for end to end complete VLSI design flows and post silicon design team support. Spearheaded configuration control for all logic, verification teams, drove design reviews, and managed design and enhancement JIRA bugs for stakeholder teams Successfully managed Product Lifecycle Management, Continual Improvement with CMMI process adherence and completed quality audits timely. Background includes full range of company sizes from startup, to mid, to large in hands on, lead, technical management, project and program management roles. Working across geographies with Japan, APAC, Europe, LA and USA stakeholders to keep project development continue round the clock.

Experience

21 yrs 6 mos
Total Experience
3 yrs 5 mos
Average Tenure
8 mos
Current Experience

Qualcomm

Program Manager Staff

Oct 2025Present · 8 mos · India

Business StrategyEnterprise Risk ManagementGovernance, Risk Management, and Compliance (GRC)Hardware EngineeringIntegrated Circuits (IC)Leadership+5

Sankalp semiconductor - hcl technology

2 roles

Associate Director

Nov 2018Oct 2025 · 6 yrs 11 mos

  • IP Design Team
Component DesignIP developmentIP SolutionsPower DistributionProblem SolvingDesign Development+17

Asso. General Manager

Nov 2018Oct 2025 · 6 yrs 11 mos

  • Program management and delivery ownership for Full chip programs.
Component DesignIP developmentIP SolutionsPower DistributionProblem SolvingDesign Development+16

Wd, a western digital company

Manager

Oct 2016Nov 2018 · 2 yrs 1 mo · Bangalore

  • Managed Design team Memory Datapath, IO and ESD.
Component DesignIP developmentIP SolutionsPower DistributionProblem SolvingDesign Development+13

Intel corporation

4 roles

SOC Design Engineer

Mar 2015Jun 2016 · 1 yr 3 mos

  • PCIe
Component DesignIP developmentIP SolutionsPower DistributionProblem SolvingDesign Development+8

PostSilicon Design Validation

Apr 2013Mar 2015 · 1 yr 11 mos

  • Memory Power Management, EV - KX4/KX/KR
Problem SolvingProcess AlignmentHardware EngineeringTechnical DiscussionsPresentationsProduct Requirements+1

Manager

Aug 2011Mar 2013 · 1 yr 7 mos

Component DesignPower DistributionProblem SolvingDesign DevelopmentProcess AlignmentHardware Engineering+12

Project Leader - Analog Design

Oct 2010Aug 2011 · 10 mos

  • Analog Design
Component DesignPower DistributionProblem SolvingDesign DevelopmentHardware EngineeringPresentation Skills+8

Amd

SDE

Jan 2009Oct 2010 · 1 yr 9 mos

  • Project Lead - Clock distribution
Component DesignPower DistributionProblem SolvingDesign DevelopmentHardware EngineeringPresentation Skills+6

Edison

Sr. Design Engr.

Apr 2006Jan 2009 · 2 yrs 9 mos

  • Full Chip DRAM design and Simulation
  • Architecture, Power and Timing Parameter Estimation.
  • Custom circuit design and simulation for Row path, data path, DLL design and interface. Experience in DDR1,DDR2 and DDR3 designs.
Component DesignPower DistributionProblem SolvingDesign DevelopmentHardware EngineeringPresentation Skills+5

Infineon

Design Engineer

Jul 2004Apr 2006 · 1 yr 9 mos

  • SP-SRAM, DP-SRAM Custom Circuit Design
Design DevelopmentHardware EngineeringPresentation SkillsTechnical DiscussionsPresentationsResearch and Development (R&D)+1

Education

Indian Institute of Technology, Bombay

M.Tech. — Microelectronics

Jan 2002Jan 2004

Rajiv Gandhi Prodyogiki Vishwavidyalaya

Bachelor of Engineering (B.Eng.)

Jan 1998Jan 2002

Indian Institute of Management Bangalore (IIM Bangalore)

Executive Education Program — Certification Independent Director

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