Aug 2024 – Oct 2025 · 1 yr 2 mos · Bengaluru, Karnataka, India · Hybrid

Mar 2021 – Aug 2024 · 3 yrs 5 mos · India · Hybrid

• 1. Working on Multi-stage Bootloaders (BL1, BL2, BL3x) as part of TF-A, ARM v8 (AArch32/64) Exception Levels, Learning Secure Boot and Booting to OS (Linux) using U-Boot
• 2. Graphics Power Management Firmware Architecture and Development for Intel’s Discrete Graphics Product Line (Includes Client and Server Graphics)
• 3. Cross-functional responsibilities with the FW, IP, and SoC Validation Engineering and Software teams during Pre-Si and Post-Si phases
• 4. Embedded Firmware development of overall Graphics Power Management Unit initialization/boot code, V/F scaling code, message passing like mailboxes, Thermal algorithms, and idle power management like C-states, Modern standby

Dec 2018 – Mar 2021 · 2 yrs 3 mos

• 7+ years of experience and has significant understanding in the below areas:
• 1. Silicon Bring-up, Firmware design, and development in GPU
• 2. GPU Power Management and understanding of sleep states, clock gating, voltage scaling
• 3. Cross-functional responsibilities with the System Validation Engineering and Software teams during Silicon bring-up

Dec 2016 – Nov 2018 · 1 yr 11 mos

• 1. DDR PHY FW Development, Silicon bring-up, and validation
• 2. Key role DDR PHY Bring-up and Validation for Qualcomm Incorporated mobile chipsets (Snapdragon 800/600 series)
• Cross-functional responsibilities with the Validation and Integration team and Software teams during Silicon bring-up
• Responsible for designing and developing the tool to analyze the DDR calibration data
• Responsible for analysis and debug of timing margins, system parameters for the DDR PHY interface
• Receive training for next generation DDR PHY interface and can extend support in design, Silicon Validation and debug

Mar 2015 – Nov 2016 · 1 yr 8 mos

• 1. Memory (DDR3/DDR4) subsystem characterization for DDR3 & DDR4 - based memory technology – Timing stress analysis for various timing parameters at different corners of operating voltage and frequency. Analyzing and post-processing the end result using homegrown tools
• 2. Memory (DDR3/DDR4) subsystem qualification/certification - Development and execution of qualification scripts using PERL as the coding language. Qualification tools are developed to stress the memory at the DRAM level to measure power, current, and voltage and even perform dynamic voltage and frequency slewing with variant flavors of DIMM suppliers’, capacity, DRAM density, DRAM die technology, etc. This effort is used globally on all pre-GA P-series server systems
• 3. Setting up the IBM Systems and Development Laboratory (ISDL) at the Bangalore location which includes P7/P7+, P8, and OpenPOWER systems, network setup, and logistics. Setting up of development reference test boards for memory characterization, debugging, and hardware procedure development and execution

Mar 2013 – Feb 2015 · 1 yr 11 mos

Jan 2012 – Jan 2013 · 1 yr · Bengaluru Area, India

• Cypress University Alliance and Design Partner Program
• Responsibilities:
• Designing of laboratory experiments and manuals based on different types of development boards (e.g PSoC 3, PsoC 5)
• Conducting Workshops and training seminars for prospective customers as well as various universities/colleges. Given workshop in 11 colleges which includes students, professors and industry folks.
• Analysis and maintenance of revenue and training dashboards
• Designing monthly/quarterly/yearly newsletters for potential customers of the company

Jun 2008 – Jul 2008 · 1 mo · New Delhi

• Detailed study of network security systems.