Triveni T — Product Manager
Verification Engineer with 6 years of experience in ASIC/GPU design verification. Skilled in SystemVerilog, UVM, and formal verification with expertise in building reusable testbenches, driving coverage closure, and debugging complex RTL. Hands-on with AXI, APB, SPI, and Ethernet protocols.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and GPU design.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 4 mos
Skills
- Systemverilog
- Uvm
- Verilog
- System Verilog
Career Highlights
- 6 years of experience in ASIC/GPU design verification.
- Expert in SystemVerilog and UVM methodologies.
- Proven track record in driving coverage closure and debugging RTL.
Work Experience
AMD
Senior Silicon Design Engineer (3 mos)
Imagination Technologies
Senior Hardware Engineer (9 mos)
Qualcomm
Senior Engineer (1 yr 4 mos)
Engineer (1 yr 7 mos)
Atria Logic Inc.
Design Verification Engineer (1 yr 6 mos)
MosChip Institute of Silicon Systems (M-ISS)
Internship Trainee (10 mos)
Education
Bachelors at Lingaya's Institute of Management and Technology
