Apr 2013 – Present · 13 yrs 1 mo · India · Hybrid

• Expert in Complex server SoC verification using UVM / System Verilog.
• Strong working knowledge on PCIe 3.0 PHY verification.
• Strong working knowledge in the most popular protocols like PCIe 4.0/3.0/2.0, DDR4.
• PCIe 4.0 verification at SoC, test plan creation, coverage analysis and closure, sequence
• development.
• Successfully verified and taped out the Networking SoCs targeted for Base-Station.
• DDR4 subsystem verification for Intel Networking products.
• Experience in architecting verification environment, defining verification strategies, creating and
• executing verification plan, developing the verification components and coverage development,
• analysis and closure.
• Rich Experience in developing verification environment using System Verilog HVL- UVM.
• Expert at Verification strategies, and test generation schemes.
• Good at finding bugs, analyzing and RTL debugging for the simulation failures.
• Expert at setting of constraints in the randomized simulation test bench, debugging of randomized
• simulation failure and coverage analysis.
• Mentoring and coaching junior engineers.
• Wide experience in collaborating with cross functional team.
• Enjoys being a team player.

Oct 2011 – Apr 2013 · 1 yr 6 mos · India · On-site

• PCIe3.0 PHY Verification

Feb 2011 – Oct 2011 · 8 mos · Maharashtra, India · On-site

Jun 2008 – Jan 2011 · 2 yrs 7 mos · India · On-site

• Developed PCIe Verification IP using System Verilog. Implemented DLL protocol logic, testbenches, and test suites.