durga bhargav p

Software Engineer

East Godavari, Andhra Pradesh, India9 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expertise in HBM protocol and IP UVC development.
Strong background in Verilog, System Verilog, and UVM.
Experience in developing protocols like SPI and LPDDR4.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in digital design and protocol development.

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Skills

Core Skills

VerilogUvmHbm Protocol

Other Skills

System VerilogSPI protocolDebuggingTest case developmentVery-Large-Scale Integration (VLSI)ASICSemiconductorsCLinuxPerlquesta simvcsSynopsys toolsxilinx

About

● Hands-on experience in HBM protocol and other IP UVC development ● Hands on expertise of verilog, system verilog and UVM. ● Good understanding of SPI protocol,LPDDR4 protocol. ● sound knowledge on USB 3.0 protocol

Experience

9 yrs 8 mos

Total Experience

2 yrs 1 mo

Average Tenure

3 yrs 6 mos

Current Experience

Amd

Sr silicon design engineer

Nov 2022 – Present · 3 yrs 6 mos · Hyderabad, Telangana, India

server soc team

VerilogSystem VerilogUVMHBM protocol

Cerium systems

Senior Verification Engineer

Nov 2020 – Dec 2022 · 2 yrs 1 mo · Hyderabad, Telangana, India

working as contractor in intel project

Wave computing

Verification Engineer

Jan 2019 – Oct 2019 · 9 mos · India

worked on dispatch engine is an IP interface between processor and DMA.
MY Responsibilities:
Architectural specification study.
Development of functional coverage plan and implementing.
debugging test cases and implementing new.
Played an active role in stimulation, verification coding and review of modules

Rambus

verification contractor

May 2018 – Jan 2019 · 8 mos · bangalore

worked on HBM( high bandwidth memory) PHY verification 7nm technology which supports 2.8gbs with 128 bit data width
key roles new test case development,debugging test case,Extest boundary sacan tests,macro test(markups),and customer issues resolving in the previous 14nm HBM project.

Asiczen technologies

2 roles

Digital Design Engineer

Feb 2018 – Nov 2020 · 2 yrs 9 mos

ASIC INTERN

Apr 2017 – Feb 2018 · 10 mos

done my internship and got good knowledge in verilog,system verilog and UVM methodology.
while internship i have done professional projects
Dual port ram in system verilog and UVM methodology from the scratch.
SPI protocol developed the UVC and implemented.

VerilogSystem VerilogUVM