chethan s — Product Engineer

Working as Senior Engineer in Qualcomm India Pvt Ltd. Responsible for the Vectors generation & support across projects, implementation of GLS methodology to reduce simulation time & vector memory. GLS simulations on peripherals & Provide necessary solution to root cause & solve the silicon issues on functional & characterization platform on ATE. Virtual test bench (VT) environment bring up & VT simulations along with binary/vector environment setup which will be used for binary generation for testing the processor (chip). wafer & package testing support across MDM/MSM chips •Skills: 1. GLS simulations qualifications for MDM/MSM chips 2. VT (virtual test bench) environment bring up & VT simulations for RTL & GLS based tests 3. Binary generation with optimal methods to reduce test time & vector memory 4. Implementation of new methodology for low speed peripherals to reduce bring up qualification time 5. Silicon debug at wafer and package level, Test and Production program development and Test Time Reduction. 6. AC characterization parameters measurement like setup time, hold time, propagation delay and data valid time measurement. 7. Worked on peripherals interfaces like SLIMBUS, JTAG, I2C, I2S, HSIC, SPI, SPMI, LCDC, TSIF, RFFE and SDCC. 8. Implementation of new methodology in GLS simulations to reduce overall simulation time & memory usage. Role: •Interact and co-ordinate with Design and DFT Engineers in on-site and off-shore to understand and resolve/debug device functional/characterization issues. •Remote test debug using testers in US and Singapore. •Conversion from different test languages (VCD, EVCD, STIL) to ATE format. •Developed and implemented test plans on ATE from device specifications. •Worked with the Product Engineering group to enhance production yield and reduce cost. •Verified devices Process, Temperature and Voltage corners. (27 corner testing) . Specialties: VERIGY 93K Test Platform.

Stackforce AI infers this person is a Semiconductor Test Engineering expert with a focus on VLSI and GLS methodologies.

Location: Bengaluru, Karnataka, India

Experience: 14 yrs 5 mos