Mayank Ameta — Product Engineer

Actively looking for a job opportunity in design and verification. Experienced Verification Engineer with a demonstrated history of working on SystemVerilog and Universal Verification Methodology(UVM). Engineering professional with a Bachelor's Degree focused in Electronics and Communication. HDL: Verilog HVL: System Verilog TB Methodology: UVM Protocol: AMBA-AXI4, AHB, SPI

Stackforce AI infers this person is a Verification Engineer specializing in digital design and verification methodologies.

Location: Bengaluru, Karnataka, India

Experience: 5 yrs 5 mos