Shivangi Goel — Software Engineer
Experienced Design Verification engineer with a demonstrated history of working on CXL Verification IP development, coverage driven constrained random verification. Skilled in Verification methodologies like UVM and OVM, system Verilog, Verilog. Exposure to EDA industry tools like VCS, Questa, Xcelium, Verdi, verification traceability via functional coverage and test plans with Verification planner.
Stackforce AI infers this person is a Design Verification Engineer in the EDA industry with a focus on ASIC and CXL technologies.
Location: Bangalore Urban, Karnataka, India
Experience: 6 yrs 8 mos
Skills
- Asic Verification
- Universal Verification Methodology (uvm)
Career Highlights
- Expert in CXL Verification IP development.
- Proficient in UVM and OVM verification methodologies.
- Strong background in ASIC verification and debugging.
Work Experience
Qualcomm
Senior Lead Engineer (1 yr 7 mos)
Synopsys Inc
R&D Staff Engineer (7 mos)
R&D Engineer Sr I (4 mos)
R&D Engineer (4 yrs 2 mos)
Education
BTech - Bachelor of Technology at Motilal Nehru National Institute Of Technology
