Shubhi Garg — Software Engineer
9 years of experience in field of RTL development, front end implementation including timing constraints development, synthesis, cdc/lint/rdc checks, and Static Timing analysis.
Stackforce AI infers this person is a Digital Design Engineer with expertise in ASIC and VLSI technologies.
Location: Delhi, India
Experience: 8 yrs 6 mos
Skills
- Application-specific Integrated Circuits (asic)
- Static Timing Analysis
Career Highlights
- 9 years of experience in RTL development.
- Expert in Static Timing Analysis and ASIC design.
- Strong background in front-end implementation.
Work Experience
Synopsys Inc
Staff ASIC Digital Design Engineer (5 yrs 4 mos)
Cadence Design Systems
Product Validation Engineer (1 yr 5 mos)
NVIDIA
ASIC Design Engineer (1 yr 9 mos)
Education
Bachelor of Technology (B.Tech.) at Delhi Technological University
at Arwachin Bharti Bhawan Senior Secondary School
