Himanshu Patel

Software Engineer

Bengaluru, Karnataka, India14 yrs experience
Highly Stable

Key Highlights

  • Expert in digital logic design for ARM-based CPU subsystems.
  • Proven leadership in driving designs from tape-out to post-silicon debug.
  • Specialized in low-power design methodologies and power management.
Stackforce AI infers this person is a semiconductor design expert with a focus on digital logic and low-power systems.

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Skills

Core Skills

Digital Logic DesignLow Power DesignAutomationQuality Assurance

Other Skills

HBM2E Phy IPPCIe Gen3 Phy IPCDCLintDebuggingPCIe Gen3Quality ChecksTiming CharacterizationAutomation FlowsPerl ScriptingCharacterizationSimulationsStatic Timing AnalysisLogic SynthesisFunctional Verification

About

• Expertise in designing and implementing complex digital logic blocks for ARM-based CPU Subsystems • Specialized expertise in CPU power management, including Boot, Idle Power Management and DVFS • Strong understanding of system-level architecture, integration, and low-power design methodologies. • Proficient in handling multi-power domain and multi-clock domain design • Strong in Digital Logic Design with in-depth knowledge of Verilog/Sys-Verilog • Proven leadership experience in driving CPUSS designs to tape-out to post-silicon debugs. • Expertise in design and development of many critical block for HBM Phy IP. • Familiar with computer architecture concepts and cache coherency principles • Hands-on with CHI interface design and ECO implementation • Extensive experience with CHI, AXI, APB, AHB protocols • Strong exposure to STA, various synchronization techniques and timing closure techniques • Skilled in CDC, RDC, Lint, and frontend quality checks • Excellent automation and scripting (PERL, TCL, Shell) • Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment Specialties: Verilog, Sys Verilog, low power design, Lint, CDC, STA, CHI, AXI, AHB, APB, Perl, Tcl, Shell scripting

Experience

14 yrs
Total Experience
6 yrs 5 mos
Average Tenure
1 yr 2 mos
Current Experience

Astera labs

Principal Engineer

Apr 2025Present · 1 yr 2 mos · Bengaluru, Karnataka, India · On-site

Qualcomm

Staff Engineer

Oct 2020Apr 2025 · 4 yrs 6 mos · India

Intel corporation

2 roles

Sr. IP Logic Design Engineer

May 2013Oct 2020 · 7 yrs 5 mos

  • Owned the design and development of many critical features in HBM2E Phy IP for Intel's first 10nm GPU Arctic Sound. (HBM IO is high performance 3D stacked DRAM interface designed for In Package Memory Support)
  • Responsible for overall development and enhancements of many critical fetures for the HBM Phy IP.
  • Worked on PCIe Gen3 Phy IP, owned complete CDC and Lint for the PCIe IP.
  • Debugged and resolved multiple functional and timing issues.
HBM2E Phy IPPCIe Gen3 Phy IPCDCLintDebuggingDigital Logic Design+1

Intern

Jun 2012May 2013 · 11 mos

  • Carried out a project on “QUALITY CHECKS AND VALIDATION OF MEMORY IP”
  • Supported design engineers for running timing characterization flow for memory compilers.
  • Design and develop automation flows as required for design engineers & layout engineers
  • Developed IP collateral Comparator and IP delivery checker.
  • Developed numerous utility scripts in Perl to enhance quality and team productivity.
Quality ChecksTiming CharacterizationAutomation FlowsPerl ScriptingAutomationQuality Assurance

Education

Nirma Institute Of Technology

M.Tech — VLSI Design

Jan 2011Jan 2013

South Gujarat University

Bachelor of Engineering (B.E.) — Electronics and Communications Engineering

Jan 2005Jan 2009

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