DURGAPRASAD MAHIPALA

Software Engineer

Bengaluru, Karnataka, India10 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Static Timing Analysis and Physical Design.
  • Proven track record in timing closure for complex semiconductor projects.
  • Strong foundation in VLSI System Design from a prestigious institution.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and timing analysis.

Contact

Skills

Core Skills

Static Timing AnalysisPhysical DesignTiming ClosureSynthesisSoc

Other Skills

LECSTAPNRPV checksCLPIR drop analysisMemory functionality verificationSoC implementationModem integrationDebuggingVHDLVerilogperlLinuxtcl

About

Experienced Electronic Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Perl, Verilog, VHDL, TCL, Synthesis & logic equivalence checking, Static Timing Analysis & Physical Design. Strong engineering professional with a Master’s Degree focused in VLSI System Design from NIT Warangal.

Experience

10 yrs 8 mos
Total Experience
2 yrs 8 mos
Average Tenure
2 yrs 9 mos
Current Experience

Infineon technologies

Senior Staff Design Engineer

Sep 2023Present · 2 yrs 9 mos · Bangalore Urban · Hybrid

  • STA engineer
Static Timing Analysis

Qualcomm

Senior Lead Engineer

Aug 2020Aug 2023 · 3 yrs · Bengaluru, Karnataka, India

  • Synthesis and Pre Layout STA lead.
SynthesisStatic Timing Analysis

Cypress semiconductor corporation

3 roles

Staff Design Engineer

Promoted

Apr 2019Aug 2020 · 1 yr 4 mos

  • Worked on Physical design aspects of timing critical blocks as well as flow updates
  • Worked on Block level timing closure for all modes including setting up mode constraint aspects
  • Worked on TOP level timing closure aspects as well as TOP STA flow bringup aspects
  • Worked on Setting up the tweaker flow for TOP as well as for blocks. Fixed all mode all corner timing violations through tweaker and given fixes to respective owners.
Physical DesignTiming ClosureLEC

Senior Electronic Design Engineer

Apr 2018Mar 2019 · 11 mos

  • Worked on Synthesis, LEC.
  • Worked on STA timing closure
  • Worked on PNR and PV checks
  • Worked on CLP and block level IR drop analysis
SynthesisLECSTAPNRPV checksCLP+1

Electronic Design Engineer

Jun 2016Mar 2018 · 1 yr 9 mos

  • Worked on Synthesis, LEC & Formality.
  • Worked on STA timing closure
SynthesisLECSTA

Broadcom limited

Tech Intern Masters

Jun 2015May 2016 · 11 mos · Bengaluru Area, India

  • Memory functionality verification
  • Implementation of full chip SoC on palladium
  • SoC level Modem integration
Memory functionality verificationSoC implementationModem integrationSoC

Education

NIT Warangal

Master’s Degree — VLSI System Design

Jan 2014Jan 2016

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