Dr. Satish kumar Grandhi

Consultant

Bengaluru, Karnataka, India17 yrs 5 mos experience

Key Highlights

  • Expert in Integrated Circuit Design and EDA tools.
  • Led power analysis for next-gen automotive IPs.
  • Developed IO characterization flow from scratch.
Stackforce AI infers this person is a VLSI Design expert with a strong focus on Integrated Circuit Design and EDA methodologies.

Contact

Skills

Core Skills

Integrated Circuit DesignPower AnalysisVlsiEdaAlgorithms

Other Skills

PowerSynthesisSTAImplementationDSPPath Based AnalysisGate Level ModellingRTL CodingIO CharacterizationSTDCELLIO Library CharacterizationLibrary CharacterizationVerilogSynopsys Tool SuiteRTL2GDS

About

Areas of interest - System design - ASIC flows & EDA

Experience

17 yrs 5 mos
Total Experience
2 yrs 2 mos
Average Tenure
--
Current Experience

Freelance

Consultant

May 2024Sep 2025 · 1 yr 4 mos · Hybrid

Career break

Personal goal pursuit

Sep 2023Apr 2024 · 7 mos

  • Spending the free time to connect more with my 2 kids
  • Brushing up a bit on financial stuff
  • Little bit of travel

Rivos inc.

Design Engineer

May 2022Aug 2023 · 1 yr 3 mos · Bengaluru, Karnataka, India

  • The worst company I ever worked for

Qualcomm

2 roles

Staff Design Engineer

Jun 2019Apr 2022 · 2 yrs 10 mos

  • Power, fishtail, synthesis, STA
  • Power lead for next gen auto IP
  • Next gen auto SOC Synth lead for 25 IP's
  • Supported power analysis activities for different mid tier snapdragon SOC's
PowerSynthesisSTAIntegrated Circuit DesignPower Analysis

Staff Design Engineer

Apr 2017May 2019 · 2 yrs 1 mo

  • First Implementation engineer at Qualcomm Ireland and set the flow for entire front end implementation activities.
  • Worked on multiple generation sensor subsystem related implementation activities.
  • Supported implementation activities for DSP block
ImplementationDSPIntegrated Circuit DesignVLSI

Synopsys inc

Senior R&D Engineer

Feb 2016Mar 2017 · 1 yr 1 mo · Ireland

  • The best team and the best company I worked with. All good PhD and very brainy batch. Worked on cutting edge algorithms dealing with Path Based Analysis. It is so much fun to deal with memory related constraints instead of power and timing.
AlgorithmsPath Based AnalysisEDA

University college cork, ireland (ucc)

Research Student

Feb 2013Jan 2016 · 2 yrs 11 mos · Ireland

  • Focus of study extends to various domains namely gate level modelling, RTL coding for IP development, EDA tool design methodology and most importantly logic synthesis tool development. I have interacted with multiple sharp minds spread across the Europe & the USA.
Gate Level ModellingRTL CodingIntegrated Circuit DesignEDA

Cypress semiconductor corporation

Senior Design Engineer

Sep 2011Jan 2013 · 1 yr 4 mos · Bengaluru, Karnataka, India

  • Setup the IO characterization flow from scratch
  • Presented my work as a paper in the internal conference "CITEC"
IO CharacterizationIntegrated Circuit Design

Nxp/cypress/iisc/nitk/stmicro

Contract Roles

Aug 2007Aug 2011 · 4 yrs · Bengaluru, Karnataka, India

  • Worked on various assignments like
  • o STDCELL & IO library and testchip characterization
  • o Timing, Power & Noise Models
  • o Setting up tool flows from scratch
  • o Teaching undergrad & Grad students
  • o MEMS based research which resulted in reputed journal paper
STDCELLIO Library CharacterizationIntegrated Circuit Design

Intel corporation

Student Intern

Jun 2006May 2007 · 11 mos · Bengaluru, Karnataka, India

  • Worked on my masters thesis on IA32 architecture and RAS feature validation

Education

University College Cork

Doctor of Philosophy (Ph.D.) — Microelectronics

Jan 2013Jan 2016

National Institute of Technology Karnataka

Master of Engineering (MEng) — VLSI Design

Jan 2005Jan 2007

Anil Neerukonda Institute Of Technology & Sciences

Bachelor of Engineering (BE)

Jan 2001Jan 2005

Stackforce found 100+ more professionals with Integrated Circuit Design & Power Analysis

Explore similar profiles based on matching skills and experience