Jun 2017 – Jun 2019 · 2 yrs · Noida Area, India

• Veloce (Emulation) –
• Mentor Graphics, Noida
• Responsibilities:
• Verification of different Veloce flows and language specific constructs.
• Specifications development of key features and working closely with development team.
• Automation of different scenarios to validate the regressions in TCL/Perl/Shell
• Projects:
• RTL Trigger - Trigger allow the detection of a given state of logic during emulation. You can control trace storage, stop emulation, execute TCL callback on emulation stopped by a trigger, and see a specific sequence of events during emulation based on the detection of specific state conditions.
• Transactor Based XRTL modeling – Create c-model of Verilog/VHDL/SV synthesizable constructs for their mapping on hardware.
• Activity analysis – Activity analysis through different stimulus formats (SAIF/CRD). Performance measurement and accuracy comparisons were carried out. This involved challenge of big data handling, and enhancing my automation skills (Bash, Perl). Related features are SAIF suspend-resume, instance list-based SAIF generation, activity profiling, crd2vcd and crd2csv.
• Veloce Flows – Worked on different compile and runtime flows such as velclockgen (frequency-based clock specification), xwave generation, record-replay, TB-replay and xcapture-xreplay.

Oct 2014 – May 2017 · 2 yrs 7 mos · Noida Area, India

• Genus (Synthesis tool) and Joules –
• Cadence Design Systems, Noida
• Responsibilities:
• Front-end language Features – Testing front-end language (Verilog/system Verilog) specific features
• Debugging customer design failures and creating small testcases for quick solution TAT.
• Synthesis benchmarking and debugging QOR degradation issues.
• Automated regression-based testing using Perl and summarize results.
• Tool Coverage Analysis - Automated commands and options coverage
• Command testing for Joules features.

Jan 2014 – Sep 2014 · 8 mos · Noida Area, India

• 1. Got hands-on experience on topics like Systm Verilog, Verilog, FPGA, and Linux, TCL.
• 2. Worked at Verification of 8 bit Arithmetic Processor using System Verilog.
• 3. Presently Working at VLSI architecture for Secure HASH generator using Verilog HDL on Xilinx Spartan 3E FPGA kit using Chip Scope Pro Analyzer.
• 4. Interfaced PS2 keyboard, VGA and UART with Xilinx Spartan 3E FPGA kit.
• 5. Verilog Coding of Adaptive Traffic Light Controller & implemented on FPGA kit.
• 6. Worked on Design and Implementation of Serial Peripheral Interface in Verilog.
• 7. Worked on project UART (Universal Asynchronous Receiver and Transmitter) with FIFO Buffer in Verilog.