Feb 2013 – Jul 2016 · 3 yrs 5 mos · Portland, Oregon Metropolitan Area

• Design manager responsible for Power Management (PM) RTL and backend design, for Intel’s mobile SOCs. Directly responsible for managing 10 engineers and dotted line responsibility for more than 40 additional engineers as part of virtual teams. Stepping manager for mobile SOCs.
• ▪ Led a team of more than 35 engineers spanning architecture, RTL design, validation and firmware and developed a parameterized and scalable power management system catering to multiple derivative SOCs, in a very constrained timeline. Broke up the feature set into a staging plan in 6-week increments and drove the feature development. Worked with architects and BU on making the right trade-offs between features and schedule. All PM features were coded, validated and enabled on the A0 stepping, keeping PM off the project critical path.
• ▪ Focused on high quality validation of key PM features prior to A0 Tape-In to ensure smooth bring up of PM features on A0 Silicon. Worked closely with validation team on determining the right mix of dynamic vs. formal verification strategies for various PM features.
• ▪ Built a high performing team from the ground up. Team delivered Power Management backend designs as well as backend designs for various SOC IPs (PCIE and UFS).
• ▪ Stepping manager for mobile SOC steppings, driving Tape-In activities including various integration, convergence and quality metrics. Focused on delivering high quality TTM product to customers to enable on-time launch.
• ▪ Helped solve various SOC design problems in a technical capacity. Fishtail timing constraint verification and clock stamping in some of the more challenging IPs and more.

Mar 2009 – Jan 2013 · 3 yrs 10 mos · Portland, Oregon Metropolitan Area

• Individual contributor in the client CPU design team. Progressed through various roles of increasing scope and responsibility spanning RTL front end through physical design.
• ▪ Intel 5th Generation Core on 14nm: Worked as Uncore RLS (Synthesis and APR) expert. Owned physical design for multiple Power Management blocks. Championed and drove conversion of legacy hand-drawn structured data-path designs, into synthesizable designs, to enable execution with velocity and efficiency. Re-coded RTL to make it synthesis friendly, and pioneered and enabled relative-placement methodology to aid timing convergence. Worked on a ICC-DP pilot project to converge one of the units using automation and eliminating manual data-path designs for enabling rapid execution and die-size optimization.
• ▪ Intel 4th Generation Core on 22nm: Power Management: Owned the RTL/microarchitecture for key features of the Power Control Unit (PCU), which was tightly coupled with the newly introduced on-chip Fully Integrated Voltage Regulators (FIVR). Worked closely with the architecture and firmware team on implementing various features including voltage/frequency changes (TURBO), active and idle power management and thermals. This client design with integrated FIVR represented a radical shift in what OEMs were enabled to do with Intel client platforms via small form-factors, and high performance per watt. Was sought after as an RLS expert for helping with convergence on Uncore physical designs.

Dec 2001 – Feb 2009 · 7 yrs 2 mos · Portland, Oregon Metropolitan Area

• Individual contributor in the client CPU design team. Progressed through various roles of increasing scope and responsibility spanning RTL front end through physical design.
• ▪ Intel 1st Generation Core on 32nm: RLS/PD expert mentoring several junior engineers for high frequency flop-based and latch-based designs in the Uncore. Mentored and led a virtual team of 20 engineers to get sequential repeaters synthesized and implemented across the Uncore.
• ▪ Intel 1st Generation Core on 45nm: Owned RTL/microarchitecture for key features of Memory Execution Unit (MEU) and was the RLS expert for the MEU. Worked on RTL for pipelined design for Store Buffer (Memory Order Buffer), which is one of the more complex and timing critical units in the MEU. Owned the RTL for MBIST and other DFX logic across the Memory subsystem. Delivered high quality, synthesis, timing and layout friendly RTL. Worked on RLS for Store Buffer and other latch-based high frequency designs. Was the physical design expert and sought after for addressing RTL as well as synthesis issues across the MEU.
• ▪ Intel Pentium 4 on 65nm: Responsible for Sea-Of-Cells Megablock RLS/PD for latch-based high-frequency design.
• ▪ Intel Pentium 4 on 90nm: RTL cluster model builder. Merged code from multiple RTL coders, addressed build and simulation issues and released RTL models on a regular cadence, to be consumed by the validation and backend teams. Consistent cadence of RTL model releases ensured steady progress on all axes of design development.