Apr 2022 – Jul 2024 · 2 yrs 3 mos · Bengaluru, Karnataka, India · Hybrid

• At Intel, I lead a team of 20 engineers to implement high-speed Interface Mini SOC test chips. I owned the closure for the MiniSOC in all aspects including bump planning, ESD closure, floorplan, placement, design routability, timing, physical verification, IR drop and other reliability flows, delivering the testchips predictably as per the schedule. I also drove the timing methodology, closure discussions for various testchips across the org and brought innovation through methodology development, leveraging VLSI design tool features to deliver robust solutions. My contributions in Project Management ensured the timely completion of critical deliverables, while my team leadership, mentoring and collaboration skills helped in building a high performance, resilient team and a productive work environment.

Oct 2021 – Apr 2022 · 6 mos · Bengaluru, Karnataka, India

• During my tenure at AMD, I led a core physical design team, which owned the implementation of advanced processors for various segments. I worked closely with engineers to meet the SOC Design metrics and optimizing performance across various TSMC nodes. My work involved extensive use of VLSI Design Tools. Team Leadership and effective Communication were key to successfully managing cross-functional teams.

Dec 2015 – Jan 2021 · 5 yrs 1 mo · Bengaluru, Karnataka, India

• At Intel, I focused on IP Design and implementation, fullchip clocking and power optimization across SOC. I led the development of a 7-partition IP design from synthesis to signoff. I also contributed to microarchitecture/RTL design of a vision IP and its physical implementation. I was instrumental in driving Innovation, contributing to several patents, and recognized for the leadership initiatives.

Apr 2014 – Dec 2015 · 1 yr 8 mos · Greater Hyderabad Area

• Performed research on wide variety of areas covering VLSI architectures, digital & mixed signal circuit design and device modeling. Delivered VLSI courses to Bachelor, Master and research students. Guided many students for their graduate theses. The research resulted in multiple publications in some of the top journals.

Apr 2013 – Mar 2014 · 11 mos · Bengaluru, Karnataka, India · On-site

• As an Advisory R&D Engineer at IBM, my focus was on Methodology Development for ASIC Design, specifically in Timing Optimization and Power Efficiency. I worked on post-route timing closure and power recovery flows for advanced processors. Improving tool flows and helping designers get a quick resolution on the issues seen were the critical expectations of the role.

Oct 2012 – Mar 2013 · 5 mos · Berkeley, California.

• Worked on developing Compact models for FinFET and UTBSOI devices in BSIM group. While at UC Berkeley, owned the deveopement of BSIM-IMG and resolved multiple issues seen by customers for BSIM-SOI models. The research resulted in multiple publications.

Jul 2009 – Dec 2009 · 5 mos · Bengaluru, Karnataka, India

• At Broadcom, I worked on ASIC physical Design for two WLAN router chips. My role involved synthesis, floorplanning, place and route and delivering clean GDS for tapeout,

Aug 2008 – May 2009 · 9 mos · Bengaluru, Karnataka, India

• During my time at Freescale, I led physical design for WiMAX and DDR2
• modules. Role involved working on the IP from off-shore external customers and own the implementation, timing convergence and delivered clean GDS for full-chip integration.

Jun 2003 – Aug 2008 · 5 yrs 2 mos · Bengaluru, Karnataka, India

• In my early career at Intel, I contributed to Physical Design and SOC Design, focusing on Timing Optimization and Power Efficiency for 45nm, 65nm and 90nm chipsets. I developed Methodology for crosstalk closure, timing gaurdbands for aging degradation, RLS based IRdrop analysis for IO clusters, timing correlation between Astro and primetime. Innovation and Collaboration were vital in achieving the design goals, and laid the foundation for my subsequent roles in the industry.