Pushpendra Yadav — CTO

- 16+ Years of total industry experience in RTL2GDS Flow. - Completed 20+ SoC Tap-Outs successfully for various technologies nodes from 4nm to 145nm. - Good exposure to lead Timing signoff Activities/Teams. - In-depth experience in Static Timing Analysis, Mixed Signal-Static Timing Analysis (MS-STA), Voltage - Aware STA (VASTA), Vmin Analysis, Synthesis, Power Analysis, Timing Constraints Development, and IO Timing. - In-depth experience from RTL to GDS flow for SoC/IPs. - Worked for SOC/IPs for Server SoC, Modem (4G & 5G), Set-top-box, Digital TV, Mobile, and USB Hub & IoT applications. - Proficient in Low power design implementation using UPF/CPF flow and Power signoff (Static, Dynamic) - Proficient in Timing Signoff of multiple instantiation module-based designs including multi-Million gate design - Experience in Logic Design, RTL coding, CMOS Design. - Good exposure on Board/Package (IO) Ring and GPIO's Muxing) design and System Level understanding.

Stackforce AI infers this person is a highly experienced VLSI design engineer specializing in SoC development and timing analysis.

Location: Bengaluru, Karnataka, India

Experience: 18 yrs 7 mos