Jul 2010 – Jun 2014 · 3 yrs 11 mos

• Development of Architecture & Microarchitecture for the functional specifications
• Individual contributor in the design tasks - RTL design, synthesis, CDC analysis, debug, verification coverage improvement in directed Verilog test environment, if needed
• Contributing actively to technical review of micro-architecture & the RTL Code
• Have good experience in control path oriented designs, asynchronous multiple clock designs
• Experience on tool flows - static timing analysis, formal equivalence checking,
• Design of IP Cores or SoC Designs for Smartphones, Tablets, 2-in-1’s etc.

May 2009 – Jun 2010 · 1 yr 1 mo

• Coordinating with the team for 40 nominees for placements involving 1200 students and 200 companies
• Planning and structuring customized training programs for the benefit of career development of IIT-Bombay talent pool
• Helping potential recruiters establish a campus presence under the Recruiter Relationship Development Program

Jul 2008 – Jun 2010 · 1 yr 11 mos

• My post-graduate research at the Centre for Excellence for Nanotechnology (CEN), IIT-Bombay was on Design and fabrication of cantilever RF MEMS inline switch for 40-60 GHz applications. It has huge potential in Mobile communications, satellite communications as its forms the core device in them.

May 2007 – Jun 2007 · 1 mo

• I worked on the Design and development of Trie Based look-up for Network Packet Processing. This was developed using verilog and successfully tested for hardware level implementation (using FPGA's)

Jul 2004 – May 2008 · 3 yrs 10 mos

• Here i did my under-graduate in the department of Instrumentation and Control Engineering. I developed keen interest in the fields of process control, control systems. With the experience as the Summer Research Intern at IIT-Madras, i developed a keen interest in the fields of VLSI Design, Digital & Circuit design.