Priyadarshi Saxena

Software Engineer

Bengaluru, Karnataka, India10 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in SERDES and memory design.
  • Proficient in VHDL and Verilog for digital design.
  • Strong background in analog design and characterization.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in analog and mixed-signal design.

Contact

Skills

Core Skills

Analog DesignMemory DesignCharacterization

Other Skills

SERDESPerformance EvaluationMemory CompilerDevelopmentCMOSSPICEFPGARTL DesignRTL CodingVLSIElectronicsCMatlabMicrocontrollersField-Programmable Gate Arrays (FPGA)

About

I am currently working as an Analog Design Engineer at Si2chip Technologies . I am presently with Global Foundries, as my client working on SERDES (mixed signal IPs) design and char, prior to this I was wprking with Qualcomm on AMS char. I have worked on SRAMs and ROM with ARM, also I have worked on Write Assists in SRAM and have experience working on VHDL, VERILOG. I am an enthusiastic person who is hungry to learn so that I can develop my self into a good engineer.

Experience

10 yrs 6 mos
Total Experience
1 yr 8 mos
Average Tenure
4 yrs 10 mos
Current Experience

Amd

3 roles

Member of Technical Staff

Jul 2024Present · 1 yr 9 mos

Sr. Silicon Design Engineer

Promoted

Jun 2021Sep 2024 · 3 yrs 3 mos

Consultant

Feb 2020May 2021 · 1 yr 3 mos

Si2chip technologies pvt. ltd.

3 roles

Senior Design Engineer

Promoted

Oct 2020May 2021 · 7 mos

Design Engineer

Apr 2018Oct 2020 · 2 yrs 6 mos

  • Design Engineer, SERDES and Memory Design and Char

Associate Design Engineer

Feb 2016Mar 2018 · 2 yrs 1 mo

  • Associate Design Engineer, Memory Design.

Globalfoundries

Consultant

Jul 2018Oct 2019 · 1 yr 3 mos · Bengaluru, Karnataka, India

Qualcomm

Consultant

Aug 2017Jun 2018 · 10 mos · Bengaluru, Karnataka, India

  • Working As a SERDES char engineer

Arm

Consultant

May 2016Jul 2017 · 1 yr 2 mos · Bengaluru Area, India

  • Memory compiler development

Silicon interfaces

Engineering Trainee

Sep 2015Dec 2015 · 3 mos

  • Taineee- VLSI Design

Hbeonlabs technologies pvt ltd

Design Engineer-VLSI (Part time)

Jan 2015Jun 2015 · 5 mos · Noida Area, India

  • I was responsible for handling B.tech and M.tech projects, development and consultation.

Education

Jaypee Institute Of Information Technology

B.Tech

Jan 2011Jan 2015

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