Sep 2023 – Nov 2024 · 1 yr 2 mos · Hybrid

• ◦ Fuse Store unit
• Added new fuses in the Fuse Store Unit. Created test plans for the newly added fuses.
• Reviewed the RTL designs for code coverage with emphasis on FSM, branch, condition, toggle and line
• coverage using Synopsys Verdi tool.
• Supported post silicon validation, boot bring-up, and driver teams with the fuse related queries such as
• valid GPU core configurations, programming spare fuses to fix the bugs.
• Simultaneously worked on RTL design of fuse store unit for various projects across integrated, discrete
• and Data Center GPU cores.
• Performed auto ECO in the Fuse Store unit using Conformal Tool.
• ◦ PFET Controller unit
• Integrated PGFSM IP into PFET controller. Added logic that interacts with Power Switches & Muxes.
• Supported the IP integration team with dangles and DFT team with ijtag integration.
• Performed unit level synthesis on the owned unit to push the RTL code into the repo after code freeze.

Jul 2020 – Sep 2023 · 3 yrs 2 mos · Hybrid

• ◦ Dispatcher controller
• Designed Dispatcher controller FSM of Power management Unit, which is responsible for controlling
• the frequency, voltage, power state changes and DVFS in various sub systems of the SoC.
• Checked the design for Lint, CDC, RDC violations during RTL design as part of the quality checks.
• Implemented unit level tests for this design to check basic functional correctness.
• Supported functional verification and firmware teams related to Dispatcher for discrete GPU projects.
• Conducted design and RTL code review meetings for the owned IP.
• ◦ SOC Power Management Architecture
• Created High level Architecture specification(HAS) for priority arbitration between Xtensa Micro con-
• troller and TAP requests.
• Created HAS for SVID(Serial voltage ID) Interface related configuration and reset exit flows followed
• by firmware during SOC reset exit flows.
• Modelled Adaptive clock modulation and Proportional-Integral-Derivative(PID) controller loop in python
• which can be used to find the best parameters that generate optimal performance.
• ◦ Parameterization of features in PM Unit
• Implemented parameter based feature addition automation, using tcsh scripting, into the VLSI design
• flow to easily add or remove a feature into a project by updating parameter. This automation generates
• project specific files corresponding to file lists, constraints, waivers, and verilog parameters & defines.
• Integrated it into RTL design signoff flow for it to be used in each project.

Jul 2019 – Oct 2019 · 3 mos · India

• TA for the NPTEL online certification course, titled "Mapping Signal Processing Algorithms to Architectures"

May 2019 – Jun 2020 · 1 yr 1 mo · Chennai, Tamil Nadu, India · On-site

• ◦ Designed and tested Channel Decoder module for the Uplink Receiver of 5G NR on Xilinx FPGA.
• ◦ Worked on end to end design flow that includes design using Vivado HLS(High Level Synthesis), Verification
• using verilog testbenches, synthesis and programming FPGA in Xilinx Vivado.
• ◦ Integrated Channel decoder into Uplink Receiver and tested the integrated design for functional correctness.
• ◦ Supported integration team during up-revisions of the receiver.

Jul 2018 – Jun 2020 · 1 yr 11 mos · Chennai Area, India

• Teaching assistant - Mapping signal processing algorithms to architectures course.
• ◦ Prepared verilog testbenches and multiple choice questions for assignments.
• ◦ Organized quiz sessions and evaluated assignment submissions and its demonstrations by the students.
• ◦ Demonstrated and documented assignment submission guidelines and procedure for vivado project exporting and importing.
• Computer organization course
• ◦ Mentored and evaluated students in the design and implementation of a pipelined CPU that supports RV32I Base Instruction Set of RISC-V ISA.
• ◦ Prepared verilog testbenches and questions for assignments.
• ◦ Organized and assisted lab sessions for this course.

Jul 2017 – Jul 2018 · 1 yr · Chennai Area, India

• Worked on a project to fix vulnerabilities present in Centive, an Incentive Application based on Java Applets.
• Developed a bank web application that can be used by bank employees to carryout transactions & process customer needs and by customers to use internet banking facilities, as a part of full stack web development training in Java programming language.