Bhargava Simhadri — Product Engineer
Career Summary : Accomplished Technology-Design Package verification expert across technology nodes, Design system qualification, Good hold over cadence spectre-ckt design tools/methodologies, IP transfer methodologies, custom layout design professional on Analog/Memory/Std cell Digital IP’s, IP-Reliability Verification, EMIR Simulation setup/maintenance and debug of flows/methodologies, IP-Physical Verification (DRC/LVS/DFM/Meth/LEF), IP- ESD convergence and sign off since 2003. Technical Capabilities : Broad spectrum of experience in Memory/Analog/std cell, custom digital interface, processor layouts. EMIR reliability Verification convergence, Setup, Debug, maintenance of flows and failure analysis. ESD compliance, verification and convergence at IP level. Experienced on advanced technology nodes up to TSMC 5nm/7nm., GF 7nm. IP level physical verification convergence. (DRC/LVS/PERK/DFM/METH/LEF) Driven the team of around 20 engineers for good amount of Analog IP’s and EMIR convergence. Circuit reliability signoff checks: modeling simulation and aging effects, soac checks. Analog Verification Tools: ADE-L and ADE-XL Tools/Methodologies/Skillset : - Cadence spectre ADE L/XL/GXL Monte Carlo simulation environments. - Virtuso Layout Editor (Cadence ), L/XL/GXL . - Apache RedHawk, Totem Cruise, Cadence Voltus Innovus-XPS/APS EMIR analysis. - Calibre RVE for DRC/DFM/Meth/LEF checks. - Calibre LVS, Synopsis icvLVS debug tools. - Apache Pathfinder for ESD verification and closure. - Synopsis Star-RC/Calibre Quantus Extraction tools Lead-Managerial Capabilities Equipped with good verbal and written communication skills. Capable of driving schedule and resource intensive projects with effective risk, Stake holder and delivery management. Can influence and drive the deliverables across Cross-Geo’s and different time zones. Flexible to pick up hands on work amidst leading teams, such as EMIR analysis, ESD sign off etc. Can hold healthy and motivational interactions with peers enabling broader opportunities. Easy to work with, quick learner, collaborate across teams and bring in the best for project execution.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Analog and Memory IP verification.
Location: Bengaluru, Karnataka, India
Experience: 22 yrs 10 mos
Skills
- Design Verification
- Analog Layout Design
- Design Automation
- Verification Methodology
- Memory Layout Design
- Project Management
- Memory Compiler Development
- Layout Verification
- Analog Design
- Power Management
- Standard Cell Design
Career Highlights
- Expert in Analog and Memory IP verification since 2003.
- Led a team of 20 engineers for successful Analog IP projects.
- Proficient in advanced technology nodes up to 5nm.
Work Experience
Cadence Design Systems
Principal Design Engineer (2 yrs 1 mo)
Infineon Technologies
Senior Staff Engineer (3 yrs 2 mos)
Marvell Semiconductor
Senior Engineer (11 mos)
GLOBALFOUNDRIES
Member Of Technical Staff (4 yrs 4 mos)
Ibm India Software Lab Private Limited
Staff HW Development Engineer (1 yr 5 mos)
Intel Corporation
Physical Design Engineer (6 yrs 9 mos)
Mask designer (4 yrs 2 mos)
Education
MS micro electronis 2009 at Birla Institute of Technology and Science, Pilani
Diploma in Electronics and Communication at MEI Polytechnic
