Basavaraj Hiremath.

Product Engineer

Bengaluru, Karnataka, India16 yrs 4 mos experience

Highly Stable

Key Highlights

Over 15 years in semiconductor memory layout design.
Led development of 3nm Nanosheet Memory compiler.
Strong expertise in project management and team leadership.

Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in memory layout and compiler development.

Contact

Skills

Core Skills

Memory LayoutCompiler Development

Other Skills

Resource ManagementUSBAnalog CircuitDDREmbedded CUnixLayoutDigital Circuit DesignRTL verificationSystemVerilogProcessorsPower ManagementDevice DriversMIPSEDA

About

Experienced Complier/Custom SRAM Memory Layout Design Engineer, 15+ years of experience with a demonstrated history of working in the semiconductors industry. Skilled in Memory Layout (compiler/custom) and Leading a team/Project Management/Building Team. Strong engineering professional with a M.Tech focused in VLSI Design & Embedded System from Visvesvaraya Technological University.

Experience

16 yrs 4 mos

Total Experience

2 yrs 7 mos

Average Tenure

6 mos

Current Experience

Meta

Silicon Engineer ( SRAM Memory - Layout)

Dec 2025 – Present · 6 mos · Bengaluru

Rivos inc.

SMTS - Silicon Layout

May 2022 – Dec 2025 · 3 yrs 7 mos · Bengaluru, Karnataka, India

Samsung r&d institute india

Senior Staff Engineer - Memory Layout

Apr 2021 – May 2022 · 1 yr 1 mo · Bengaluru, Karnataka, India

Worked on 3nm Nanosheet Memory compiler development from scratch. Did 1st test-chip tapeout for Samsung Foundry with 3nm. Managed 3 different compilers with different tech nodes and resource management.

Broadcom limited

3 roles

Memory Layout

Jul 2018 – Apr 2021 · 2 yrs 9 mos · Bangalore

R & D IC Design Engineer - 2

Feb 2015 – Aug 2017 · 2 yrs 6 mos · Bangalore

Memory Layout Design

Staff -I, IC Design

Feb 2012 – Feb 2015 · 3 yrs · Bangalore

Memory Layout Design

Invecas

Memory Layout

Aug 2017 – Jul 2018 · 11 mos · Bangalore

Memory Layout Design

Netlogic microsystems

IC Layout Design Engineer

Feb 2010 – Feb 2012 · 2 yrs · Bangalore

Worked as Memory Layout Design Engineer, was supporting to Netlogic + RMI products.

Bsk information technology india pvt ltd

Graduate Intern

Apr 2008 – May 2009 · 1 yr 1 mo · Bangalore, India

Worked as Graduate Intern. Mainly worked on Analog and Mixed signal Design.

Education

Visvesvaraya Technological University

M.Tech — VLSI Design & Embedded System

Jan 2007 – Jan 2009

HIT, Nidasoshi, Belagavi

B.E — Electronics and Communication

Jan 2002 – Jan 2006

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