Shruthi GS — Software Engineer

My professional experience in the industry is 13+ years in DFT -> Strong experience in DFT architectures of JTAG, Scan Compression Techniques, scan insertion for verification for large SoC designs -> Experience generating scan patterns and coverage statistics (low coverage analysis) for various fault models; stuck at, Transition faults, path-delay . -> MBIST insertions and integration. -> INTEST and EXTEST architectural knowledge and ATPG at SOC level. -> Skilled in post silicon debug and working experience with ATE Tester Team. Exposure to debugging tester failures of scan patterns, diagnosis and pattern re-generation. -> Involved improvising testability of the design and scan chain balancing issues. -> Knowledge of industry standard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent tools etc). -> Good understanding of constraints development for PD/STA. -> SPYGLASS DFT and fishtail . -> BSDL RTL generation and validation. -> Strong written and verbal communication skill with the ability to explain and present complex ideas in simple format. -> Skilled is Perl scripting. Specialties: Specification to Tape-out, DFX RTL implementation to ATPG pattern testing/debug on Silicon, flawless execution.

Stackforce AI infers this person is a DFT expert with extensive experience in semiconductor testing and verification.

Location: Bengaluru, Karnataka, India

Experience: 14 yrs 8 mos