Ratheesh Thekke Veetil

Director of Engineering

Bengaluru, Karnataka, India20 yrs 9 mos experience

Highly Stable

Key Highlights

18+ years of experience in DFT domain.
Led successful A0PRQ for over 20 SoCs.
Expertise in FuSa compliant SoCs DFT strategies.

Stackforce AI infers this person is a DFT Architect specializing in semiconductor design and testing.

Contact

Skills

Core Skills

DftSocTest Constraint DevelopmentAtpg

Other Skills

debuglbistmbistAutomatic Test EquipmentVerilogICSemiconductorsSiliconRTL designProduct EngineeringStatic Timing AnalysisBoundary ScanTestingPhysical DesignVLSI

About

18+ years of Industry experience in DFT domain with 20+ SoCs successful A0PRQ (First Silicon Pass). Expertise in DFT Architecture definition of complex IPs/SOCs in ADAS, Client, Server, IOTG, Micro Controller segments. Hand-on experience in multiple areas of DFT domains includes SCAN/ATPG, MBIST, Boundary Scan, Analog/Phy DFT, Test STA Constraints, Pattern delivery and Tester debug. Expertise in defining and driving in-field self-test Architecture and DFT strategies for FuSa compliant SoCs. Along with owning DFT, I own the ARM-based Debug Architecture for heterogeneous core SoCs, which supports all silicon debug activities for the SoC.

Experience

20 yrs 9 mos

Total Experience

4 yrs 5 mos

Average Tenure

3 yrs

Current Experience

Analog devices

Director

Jun 2023 – Present · 3 yrs · Bengaluru, Karnataka, India · Hybrid

Ownership of multiple SoC's DFT
DFT Lead and Architect
SoC Debug (ARM - CoreSight based) Architect

debugDFTSoC

Intel corporation

DFT Architect/Senior Engineering Manager

Oct 2016 – Jun 2023 · 6 yrs 8 mos · Bengaluru Area, India

DFT Architect: Responsible for DFT Architecture detention, Test Constraint development for multiple complex SoC (Server/Client/ADAS) including chiplets with 2.5/3D technologies.
DFT Lead: End to End (TR to Silicon Bring-up/PRQ) DFT Lead with a team of 15-25 DFT Engineer to achieve A0PRQ quality silicon

lbistmbistDFTTest Constraint development

Amd

DFT Lead

Oct 2014 – Oct 2016 · 2 yrs

Currently leading SCAN/ATPG SOC team and working with WW Platform and Product Engineering Team. Accountable in DFT schedule/resource planning for next generation product.

ATPGAutomatic Test Equipment

Texas instruments

3 roles

Lead Engineer (DFT)

Nov 2010 – Oct 2014 · 3 yrs 11 mos · Bangalore

Responsible in planning, tracking and ensuring timely and quality delivery from DFT team of 28nm designs (2 28nm complex IPs)
Worked as SOC DFT lead for 45nm design
Worked as IP DFT lead for 45nm design

Senior Design Engineer

Promoted

Jan 2008 – Nov 2010 · 2 yrs 10 mos · Bangalore

Ownership of DFT specification of SOCs and IPs
Ownership of DFT implementation and verification
Ownership of ATPG, Memory test, Boundary scan, Low pin count/Low cost test etc... activities
worked with cross domain - Product engineering, Physical design and RTL team
Silicon bring-up experience of multiple SOCs in different technology nodes