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chinmaya V

Product Manager

Bengaluru, Karnataka, India6 yrs 3 mos experience
Highly Stable

Key Highlights

  • 9+ years in Physical Design & STA domain
  • Expertise in 4nm to 16nm technology nodes
  • Proficient in TCL, Perl, and Linux
Stackforce AI infers this person is a VLSI design engineer with expertise in physical design and static timing analysis.

Contact

LinkedIn

Skills

Other Skills

Low-power DesignStatic Timing AnalysisVery-Large-Scale Integration (VLSI)Physical DesignCshIcc 2Cadence EncounterPrime timeCaliberPhysical VerificationICCFULL CHIP TIMING7nm - 16nm technology nodesSTATiming

About

• Highly self-motivated individual, with an industry experience of 9+ years in "PHYSICAL DESIGN & STA" domain. • pursued experience on block level ( synthesis, Pnr and signoff : timing STA, DRC , DFM etc ). • proficiency in TCL, perl, Linux • worked for tech nodes 4nm , 5nm, 7nm, 10++, 14nm, 16nm

Experience

6 yrs 3 mos
Total Experience
3 yrs 1 mo
Average Tenure
--
Current Experience

Intel technologies india

SoC Design Engineer

Oct 2018 – May 2022 · 3 yrs 7 mos · India

Amd

Physical Design Engineer

Jan 2016 – Sep 2018 · 2 yrs 8 mos

  • contract employee

Education

GITAM Deemed University

Master's degree — VLSI

Jan 2011 – Jan 2013

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