Shivendra Singh

Software Engineer

Bengaluru, Karnataka, India8 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Analog Circuit Design and Mixed-Signal IC Design.
Proven experience in High Bandwidth Memory architecture.
Strong background in reliability verification for PLL IP.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Analog and Mixed-Signal IC design.

Contact

Skills

Core Skills

Analog Circuit DesignMixed-signal Ic DesignCircuit Design

Other Skills

Timing ClosureVariation AnalysisAnalog CircuitsTimingCadence VirtuosoCadence SpectreTransistorsCadenceVLSI CADCC++EldoXilinx ISEVery-Large-Scale Integration (VLSI)CMOS

About

Working on different LDO architecture and RX Block for High bandwidth memory IP. Experience of handling reliability issue. Also worked on Adaptive frequency system for PLL IP.

Experience

8 yrs 10 mos

Total Experience

1 yr 11 mos

Average Tenure

2 yrs 7 mos

Current Experience

Cadence design systems

Lead Design Engineer

Nov 2023 – Present · 2 yrs 7 mos · Bengaluru, Karnataka, India

Intel corporation

Analog Mixed Signal Design Engineer

Nov 2020 – Nov 2023 · 3 yrs · Hyderabad, Telangana, India

Working on different LDO architecture for HBM and IO communication IP. Also handling reliability verification for PLL IP and worked on Adaptive frequency system for PLL IP.
Handle the receiver block for HBM3 Phy IP for die to die communication.

Timing ClosureVariation AnalysisAnalog CircuitsTimingCadence VirtuosoCadence Spectre+3

Synaptics incorporated

Design Engineer

Jan 2019 – Nov 2020 · 1 yr 10 mos · Hyderabad, Telangana, India

Design and develop ESD structure for IO Analog block.Test and validate ESD power clamp for different projects like touch n display products and automotive products. Perform simulation and validation of ESD as well as reference generation circuits.
Handle the Linear regulator design for PLL IP. Familiar with different OPAMP Topologies and their design,compensation techniques.

Variation AnalysisAnalog CircuitsCadence VirtuosoCadence SpectreTransistorsAnalog Circuit Design+1

St microelectronics

Intern

May 2018 – Dec 2018 · 7 mos · Greater Noida

Designing and analysing the ESD Power CLAMP for different technologies(like 130nm, 180nm, 90nm, 40nm) in SOI TECHNOLOGY. Performing various Tests and Simulation like HBM test, TLP test and DC leakage current analysis.

Transistors