Sai Kumar Maddali

Director of Engineering

Hyderabad, Andhra Pradesh, India27 yrs 2 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Processor Verification and ASIC Design.
  • Proven leadership in managing cross-site engineering teams.
  • Extensive experience in RISC-V and PowerPC architectures.
Stackforce AI infers this person is a semiconductor verification expert with a focus on ASIC and processor design.

Contact

LinkedIn

Skills

Core Skills

Processor VerificationAsic Front-end Design And Verification

Other Skills

RISC-V CPU Core DVCPUSS DV Team ManagementIP/SOC Design and VerificationCPU Unit Level VerificationMemory Cluster Level VerificationP8 Server Processor Core VerificationPowerPC Embedded Processor VerificationGPON ONT/ONU Chip Design and VerificationMIPS-4KEC Core IntegrationFusiv Series VOX Network Processor Development and VerificationASIC IP Cores Design and VerificationEmbedded SystemsSystemVerilogICVerilog

About

Processor Verification ASIC Front-end Design and Verification Bus architectures and Memory Controllers VerilogHDL and VHDLCoding System Verilog, UVM and OVM Experience Domain knowledge in Processors and Networking Knowledge in Synthesis and ASIC Flow Experience in Leading Teams Co-ordinating with multi site teams Keen to develop new skills and face new challenges Specialties: Processor Verification ASIC Front-end Design and Verification VerilogHDL and VHDLCoding System Verilog, UVM and OVM Experience

Experience

27 yrs 2 mos
Total Experience
2 yrs 10 mos
Average Tenure
4 yrs 5 mos
Current Experience

Sifive

Director

Jan 2022 – Present · 4 yrs 5 mos · Hyderabad, Telangana, India

  • RISC-V CPU Core DV
RISC-V CPU Core DVProcessor VerificationASIC Front-end Design and Verification

Qualcomm

Principal Engineer/Manager

Aug 2019 – Dec 2021 · 2 yrs 4 mos · Greater Hyderabad Area

  • Managed CPUSS DV Team in Hyderabad
CPUSS DV Team ManagementProcessor VerificationASIC Front-end Design and Verification

Intel corporation

Engineering Manager

Nov 2014 – Aug 2019 · 4 yrs 9 mos · Greater Hyderabad Area

Samsung semiconductor india

Principal Engineer

Aug 2013 – Nov 2014 · 1 yr 3 mos · Bangalore, Karnataka

  • Managed IP/SOC Design and Verification Activities.
IP/SOC Design and VerificationASIC Front-end Design and Verification

Soft machines

CPU Verification Lead

Oct 2011 – Jul 2013 · 1 yr 9 mos · Hyderabad, India

  • Handled CPU Unit Level Verification and Memory (MEM) Cluster Level Verification Activities for Load-Store Queue (LSQ), Memory Management Unit (MMU), Cache Sub-System and Bus-Interface Unit (BIU).
CPU Unit Level VerificationMemory Cluster Level VerificationProcessor Verification

Ibm

Senior Staff Engineer, Processor Verification

Apr 2008 – Oct 2011 · 3 yrs 6 mos · Bangalore

  • Worked on P8 Server Processor Core and Chip Verification
  • Earlier I was Responsible for Leading Level-3 Support Technical Team from IBM Bangalore Design Center
  • Worked on PowerPC Embedded Processor 4XX Cores (PPC464FP, PPC476FP) Verification & Supported PPC405S and PPC440 Cores
  • ASIC IP/Core Development, Verification, Delivery and Support
  • VMC Smartmodels Development, Delivery and Support
  • AVP Programs (Architectural Verification Programs) Development, Delivery and Support
  • Handled IBM External Customer Issues on PPC4XX Cores
  • Provided Technical Support to IBM PowerPC Support Level-2 Teams
  • Collaborating with IBM Global Teams in US and Japan
  • Co-Ordinating and Communicating Level-3 India Team Status to IBM USA Team
P8 Server Processor Core VerificationPowerPC Embedded Processor VerificationProcessor Verification

Transwitch india pvt ltd, new delhi, india

Senior Member Technical Staff

Aug 2006 – Apr 2008 · 1 yr 8 mos

  • Worked as a Technical Lead
  • Involved in GPON ONT/ONU Chip Design and Verification Activities
  • Integrated MIPS-4KEC Core into Control Processing Engine and DSP Processing Engine and Carried Sub-System and System Verification
  • DDR2 Controller Command-Reordering Algorithm IP Development and Verification
  • End-to-End System Level Verification Activities
GPON ONT/ONU Chip Design and VerificationMIPS-4KEC Core IntegrationASIC Front-end Design and Verification

Ikanos communications

Senior ASIC Design Engineer

Feb 2006 – Jul 2006 · 5 mos

  • Worked on Fusiv Series VOX Network Processor Chip Development and Verification
Fusiv Series VOX Network Processor Development and VerificationASIC Front-end Design and Verification

Analog devices

Senior ASIC Design Engineer

Apr 1999 – Feb 2006 · 6 yrs 10 mos

  • Worked on Fusiv Series VOX (Voice Over XDSL) Network Processor Chips (VOX200, VOX150, VOX160 and VOX160CK) Development and Verification
  • Worked on Unit, Sub-System and Full Chip System Level Simulations at RTL and Gate Level
  • Handled Analog Devices 218X DSP Co-Verification and BlackFin DSP-SPORT (Synchronous Serial Port) Verification
  • Test Vector Generation Activities
  • Supported Emulation and Post Silicon Validation Teams
  • Worked on IP-Sec Algorithms Development and Verification
  • Network IP Protocols Development and Verification
Fusiv Series VOX Network Processor Development and VerificationASIC Front-end Design and Verification

Chiplogic india private ltd

Member Technical Staff

Jan 1999 – Jan 2001 · 2 yrs · Hyderabad, Telangana, India

  • ASIC IP Cores Design and Verification Activities
ASIC IP Cores Design and VerificationASIC Front-end Design and Verification

Education

Devi Ahilya Vishwavidyalaya

MSc — Electronics

Jan 1996 – Jan 1998

Acharya Nagarjuna University

BSc — Electronics

Jan 1993 – Jan 1996

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