Santosh Srivatsan

Software Engineer

San Jose, California, United States2 yrs experience

Highly Stable

Key Highlights

Expertise in GPU design and verification.
Contributed to open-source Vortex GPGPU project.
Strong foundation in Computer Architecture and ASIC Design.

Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on GPU architecture and verification.

Contact

Skills

Core Skills

Graphics Processing UnitObject-oriented Programming (oop)SystemverilogVerilog

Other Skills

C++GPGPUUniversal Verification Methodology (UVM)C (Programming Language)LinuxModelSimJavaVLSI DesignArduinoNI LabVIEWProteusNetwork Simulator 3 (NS-3)Cadence VirtuosoEagle PCB

About

I’m a Computer Engineering graduate student at NC State University focusing on Computer Architecture, and ASIC Design. Previously, I worked as a Research Affiliate at the HPArch Lab at Georgia Tech where I helped contribute to the open-source Vortex GPGPU.

Experience

2 yrs

Total Experience

2 yrs

Average Tenure

2 yrs

Current Experience

Nvidia

Verification Engineer

Jun 2024 – Present · 2 yrs · Santa Clara, California, United States · On-site

Apple

GPU Design Verification Intern

May 2023 – Aug 2023 · 3 mos · Orlando, Florida, United States · On-site

Created a new UVM/SystemVerilog memory subsystem testbench and added realistic stimulus to validate the interface between two blocks.
Enhanced the robustness of existing UVM components (stimulus, checkers, etc) to accommodate the new testbench while maintaining compatibility with current test environments and improving reuse.

Graphics Processing UnitObject-Oriented Programming (OOP)

North carolina state university

Graduate Research Assistant

Aug 2022 – Dec 2022 · 4 mos · Raleigh, North Carolina, United States

• Designed VEris, a simulation-based fault injection framework that leverages the Verilog Procedural Interface (VPI) to inject faults into RTL.

C++SystemVerilog

Georgia institute of technology

Research Intern

Aug 2021 – Aug 2022 · 1 yr · Atlanta, Georgia, United States

Designed a Generic Memory Stream Reader using Verilog; Interface between the texture/raster/render output units and their respective caches.
Designed a Depth Stencil Unit and an ROP Memory Unit (that instantiates the Memory Stream Reader) for Vortex’s Render Output Unit.
Leveraged the spike/riscv–isa–sim simulator to extend vortex to support a RV64 IMFD ISA.
Implemented hardware counters (# of prefetch requests, # of unique/late/unused prefetches) to assess the performance of Vortex’s software prefetcher.
Publication – Blaise Tine, Varun Saxena, Santosh Srivatsan, Joshua R. Simpson, Fadi Alzammar, Liam Cooper, and Hyesoon Kim. 2023. Skybox: Open-Source Graphic Rendering on Programmable RISC–V GPUs. ASPLOS 2023.

C++Verilog