S S Gupta Kolluru (Naveen) — Product Engineer
13+ years of experience in Physical Design, from RTL to GDS, including formal verification, low power, physical verification, and signoff closure. Proven track record of multiple tape-outs in various nodes (90nm to 3nm). Skilled team builder and collaborator with expertise in DXIO, Memory Controller, SOCs, and Arm cores. Aspire to leverage my expertise in Physical Design to drive innovation and growth in a forward-thinking organization. Continuously learning and growing to achieve excellence in my field.
Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in Physical Design and SoC implementation.
Location: Bengaluru, Karnataka, India
Experience: 13 yrs 8 mos
Skills
- Physical Design
- Physical Verification
- Soc Design
Career Highlights
- 13+ years in Physical Design from RTL to GDS.
- Proven track record of multiple tape-outs from 90nm to 3nm.
- Expertise in DXIO, Memory Controller, and SOCs.
Work Experience
Cadence Design Systems
Principal Application Engineer (6 yrs 7 mos)
AMD
Sr Silicon Design Engineer (1 yr 9 mos)
Intel Corporation
SoC Design Engineer (1 yr)
QUALCOMM Inc
Senior Engineer (3 yrs)
eInfochips (An Arrow Company)
Physical Design Engineer (1 yr 4 mos)
Cadence Design Systems
Intern & Consultant AE (1 yr)
Education
Master's degree at Birla Institute of Technology and Science, Pilani
Bachelor's degree at Jawaharlal Nehru Technological University, Kakinada
