Bhanuprakash K R

Software Engineer

Bengaluru, Karnataka, India12 yrs 8 mos experience

Most Likely To SwitchAI Enabled

Key Highlights

Expertise in SRAM memory layout design across multiple technology nodes.
Proficient in physical verification and reliability checks.
Hands-on experience with leading EDA tools and scripting for automation.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in SRAM and physical verification.

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Skills

Core Skills

Digital Layout DesignSramMemory Layout DesignPhysical Verification

Other Skills

5nm FINFETCalibre LVSCalibre DRCLEFCNODE check7nm FINFETSRAM Pattern checkDFMMeth checkCalibre/Gemini LVS/DRCEMC Compiler PlatformLT SpiceLitho checkERCEM-IR Analysis

About

Memory Layout Design Engineer Good layout design experience in lower technology nodes 3nm, 5nm, 7nm,10nm and 28nm Experience in Digital layout Design for Custom and Compiler SRAM memories. Have good Knowlege and Hands on Experience on leafcell development, physical verification and basics of compiler coding for layout tiling and netlist generation.

Experience

12 yrs 8 mos

Total Experience

3 yrs 2 mos

Average Tenure

5 yrs 1 mo

Current Experience

Broadcom inc.

IC Design Engineer

May 2021 – Present · 5 yrs 1 mo · Bengaluru, Karnataka, India

Marvell semiconductor

Senior Engineer

Nov 2019 – May 2021 · 1 yr 6 mos · Bangaon Area, India

Technology Nodes: 5nm FINFET
Book height definition, Floor plan, Leaf cell layouts
3 port SRAM layouts for various sub blocks - Global Control and Global IO
Reliability checks - Calibre LVS, DRC, LEF and CNODE check on Instance level

5nm FINFETCalibre LVSCalibre DRCLEFCNODE checkDigital layout Design+1

Globalfoundries

Principal Product Engineer

Dec 2017 – Nov 2019 · 1 yr 11 mos · Bengaluru Area, India

Technology Nodes: 7nm FINFET
Book height definition, Floor plan, Leaf cell layouts
2 port SRAM layouts for various sub blocks - Global Control and Global IO
Reliability checks - Calibre LVS, DRC, SRAM Pattern check, LEF, DFM and Meth check on Instance level in the compiler range

7nm FINFETCalibre LVSCalibre DRCSRAM Pattern checkLEFDFM+3

Qualcomm

Consultant

Jan 2015 – Aug 2017 · 2 yrs 7 mos · Bengaluru Area, India

Technology Nodes: 7nm, 10nm FINFET
Architecture definition, Floor plan, Leaf cell layouts
SRAM (L2 cache,single port and Triple port RF) layouts for various sub blocks - Local IO, Global IO and Redundancy blocks
Reliability checks - Calibre LVS, DRC, Litho check, ERC, LEF, DFM

Calibre LVSCalibre DRCLitho checkERCLEFDFM+2

Esilicon

Contractor

Feb 2014 – Dec 2014 · 10 mos · Ho Chi Minh City, Vietnam

Technology Nodes: 28nm
Architecture definition, Floor plan, Leaf cell layouts
SRAM (single port ) layouts for various sub blocks - Local control, Global Control, Local IO, Global IO, Redundancy blocks
Reliability checks - Calibre LVS, DRC, EM-IR Analysis.

Calibre LVSCalibre DRCEM-IR AnalysisDigital layout DesignSRAM

Zia semiconductor pvt ltd

Design Engineer-I

Oct 2013 – Dec 2017 · 4 yrs 2 mos · Bengaluru Area, India

Memory Layout and Circuit Design Engineer
Memory Layout
Layout leafcell development of various sub-blocks in custom and compiler memories
Various physical verifications - LVS, DRC checks
Abutment and Boundary checks
Understanding of the post-decoder programming(via programming and placement)
Tools used : Glade Layout Editor, Calibre/Gemini LVS/DRC, EMC Compiler Platform
Node:40nm
Standard Cell Library Layout
Defining track based layout architecture
Layout designing of basic gates and complex circuits like D–flops, Mux, Adders, Subtractors, Xor, Xnor & Boolean functions
Various physical verification such as LVS, DRC checks
Node:40nm
Automation
Compiler coding for Layout tiling and Netlist generation
Perl scripting for internal automation requirements
Tools used : EMC Compiler Platform
Memory Characterization and Circuit Designing
Memory Bitcell (SRAM) and Sense Amplifier analysis
Memory Architecture & Critical Path Modelling
Timing Analysis
Perl Scripting for various Automation requirements
Tools used : LT Spice
Node:45nm