Nov 2009 – May 2013 · 3 yrs 6 mos · Hyderabad Area, India

• Responsible for all front Related implementation activities like synthesis, formality, STA and MVRC checks
• UPF development and MVRC checks at module level
• MVRC checks at SOC and Sub-System Level
• Timing closure and constraints validation
• Done Power Aware Synthesis (28nm) for Graphics Modules.
• Design Compiler Topo-Graphical Synthesis using PD DEF.
• MVRC checks on RTL and Netlist for graphics IP’s.
• Pre-PD STA in Functional mode.
• Interacted closely with RTL team for developing timing constraints
• Formality for Power aware and Non-Power aware checks for RTL Vs Netlist
• Did Functional ECO’s and Power aware ECO’s on post layout netlist.
• Developed scripts for implementing ECO’s in DC using TCL.
• Interacted with Physical Design team for congestion and placement issues to get better QOR
• Developed TCL scripts for extracting the instances for GATESIM requirements.
• Memory Generation for Different IP’s using Virage Compiler.
• Set the flow for synthesis and ECO flow.