Mar 2026 – Present · 3 mos

Aug 2011 – Mar 2026 · 14 yrs 7 mos

• Currently working on doing unit level verification of USB IP. Have good hands on experience in both XHCI and USB3.0/USB3.1 specs. End to end verification of USB Root Port based virtualization which included coverage driven verification , regression closure etc.
• Have a good experience of unit level verification/FPGA/Silicon Validation of SD/eMMC Host Controller. It involves:
• Exhaustively verifying the various advanced and high speed/DDR modes supported by the SD/eMMC Controller. Got complete understanding of the entire Design Architecture/timing/CDC crossings through this process.
• Performance analysis/verification by developing system verilog based performance monitor and analyse which particular hardware block is the bottleneck which involves complete understanding of the data path between SDMMC controller and memory interface and the device.
• Have a good understanding of the RTL design and debugging various issues seen during verification.
• Have a good hands on experience of debugging various issues seen during Silicon validation using advanced techniques.
• Have good experience of FPGA validation and debugging issues using Scope and Analyser.
• Have a good experience of developing System Verilog related BFMs.
• Have good experience of creating Unit level verification environment from scratch which involves creating unit testbench for both directed and random verification (random constraints) , functional coverage and developing DUT Model and Scoreboard.
• Have good understanding of SOC verification.
• Have worked on UHS-II protocol verification and created the complete unit level testbench from scratch.
• Have a good knowledge of the following AMBA buses:
• APB,AHB, AXI
• Skills:
• Verilog , System Verilog , UVM (Basic) , C , C++ , Perl , FPGA Validation , Silicon Validation

May 2010 – Jul 2010 · 2 mos · Bangalore