Aadil Bashir — Product Engineer
Physical Design Engineer with expertise in ASIC design flow, Static Timing Analysis (STA), and advanced FinFET process nodes (TSMC, Intel). Skilled in physical verification (DRC/LVS), timing closure, clock tree synthesis, and power optimization. Experienced in FPGA development, AMS simulation, and ECO implementation. Adept at collaborating with cross-functional teams to deliver high-quality silicon solutions on schedule. Core Skills • Physical Design: Floorplanning, Placement, Routing, Power Planning, Congestion Analysis, CTS • Verification: DRC, LVS, Antenna Checks, Reliability Verification (EM, IR drop), Parasitic Extraction • Tools: Synopsys IC Compiler II, Fusion Compiler, PrimeTime-SI, Cadence Innovus, Genus, Star-RC, Virtuoso, Tempus, Xcelium • FPGA & HDL: Xilinx Vivado, Verilog, VHDL • Tech Nodes: 7nm, 10nm, 12nm, 14nm, 45nm, 130nm, 180nm • Other: ASIC Flow, Timing Closure, PPA Optimization, ECO Implementation
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and FPGA technologies.
Location: Bangalore Urban, Karnataka, India
Experience: 3 yrs 9 mos
Skills
- Physical Design
- Fpga & Hdl
Career Highlights
- Expert in ASIC design flow and physical verification.
- Proven experience in FPGA development and AMS simulation.
- Skilled in timing closure and power optimization.
Work Experience
3rdiTech Inc.
Physical Design Engineer (2 yrs 7 mos)
Indian Institute of Technology, Delhi
Senior Project Scientist (7 mos)
Intel Corporation
Consultant Physical design (1 yr)
University of Kashmir
Internship Trainee lightweight cryptography (6 mos)
Student Research Assistant (6 mos)
ChipEdge Technologies Pvt Ltd
Physical Design Engineer (1 yr 4 mos)
Education
Master of Technology - MTech at University of Kashmir
Training at Chipedge
Bachelor of Technology - BTech at Islamic University of Science & Technology, Pulwama
at iust kashmir
12th at Jammu And kashmir state board
