Vishal Trivedi — Software Engineer

• Good understanding of ASIC verification flow. • Good programming skills in SystemVerilog and Verilog. • Good understanding and programming skills using Verification methodologies UVM. • Hands on experience with EDA tools. • Good Understanding of HVL concepts. Able to code test scenario using existing given test plan. Knowledge of HVL test bench components, debugging HVL environment. • Understanding of functional coverage metric and identification of additional scenarios. • Good programming medium complex HVL test bench modules like monitors, checker, BFMs etc., from the given verification plan and functional coverage modules based on coverage plan. • Experience of developing the verification environment using SystemVerilog and industry standard verification methodologies (UVM).

Stackforce AI infers this person is a skilled ASIC Verification Engineer with expertise in VLSI and functional verification.

Location: Bengaluru, Karnataka, India

Experience: 13 yrs 9 mos