Sainarayanan K S

Director of Engineering

Bengaluru, Karnataka, India20 yrs 6 mos experience

Key Highlights

20+ years in Physical Design and CAD methodologies.
Expertise in high performance ARM cores and Mali-GPU.
Published 20 international papers in VLSI conferences.

Stackforce AI infers this person is a Semiconductor Design Expert with extensive experience in Physical Design and CAD methodologies.

Contact

Skills

Other Skills

ASICApplication-Specific Integrated Circuits (ASIC)CMOS

About

- 20+years of experience in Physical Design from netist till GDS (including synthesis) & Timing , power & IR signoff, technology CAD - Experience in implementation of high performance ARM cores and Mali-GPU (G5X & G7X) series - Managing a team to implement high performance ARM cores and perform PPA analysis - Expanded the role to drive the high performance hard core hardening & achieving silicon success - Technical Mentorship -- Full Chip Clock Tree Implementation and Sign-off - Technology worked include 130nm,90nm,65nm,45nm,28,16 & 7nm - Technical breadth ranging from standard cell characterization, SPICE simulation, Synthesis, Place & Route, Constraint management, Timing, Power & IR closure, deciding or coming up with signoff guidelines etc. - Published around 20 International Papers in various VLSI conferences including DAC'19,VLSID'14, ISQED'08, ISVLSI'07, GLSVLSI'07, ISCAS etc

Experience

20 yrs 6 mos

Total Experience

Average Tenure

Current Experience

Marvell technology

2 roles

Director CAD Flow & Methodology

Promoted

Apr 2023 – Present · 3 yrs 2 mos

Sr.Staff CAD Manager- Central Engineering Methodology

Jun 2020 – Apr 2023 · 2 yrs 10 mos

Arm

Principal Design Engineer

Jan 2012 – Jun 2020 · 8 yrs 5 mos · Bengaluru Area, India

Working in PoP (Processor Optimization Package) Team
Implemented Quad/Dual Core CORTEX-A9/A15/A57 MP processors aiming at optimal PPA
Implementation of Mali-GPU

Amd

Senior ASIC Design Engineer

Jun 2009 – Dec 2011 · 2 yrs 6 mos

Signoff Guideline Development for Global Foundries 28nm process
Developed guidelines for
OCV numbers, Hold Fixed Margin
Power and Signal EM
PVT Corners for Timing Analysis
Performance Analysis
Repeater Analysis
Transistor Aging
Place n Route for a 28nm Test Chip
Full Chip Clock Tree Building using X & H-Tree

Teranetics

Senior Physical Design Engineer

Jan 2009 – Jan 2009 · 0 mo

Responsibilities:
Synthesizing a block of 1.1M instance complexity and
performing Logical Equivalance
Performing DFT includes BIST , scan insertion and EDT insertion
Pre-Layout STA
Performing block level physical design from floorplanning till routing
Setting up the Power and Drop Analysis flow using EPS
(Encounter Power System)
Performing Extraction and finding out the deviation between the 5
interconnect corners for coming up with derate with respect to
typical spef corner
CAA analysis and repair by wire-spreading and widening through
model based approach
Timing Analysis (STA)

Amd

ASIC Design Engineer-2

Jan 2008 – Jan 2008 · 0 mo

Here i was involved in performing block-level Place and Route for a chip targeted at 45GS technology node. Developed various utilities to ease ECO cycle. I was also responsible for performing SPICE simulation for top-level clock-tree to sign-off on skew numbers. I was also involved in developing design guidelines for 40LP process.

Conexant

Senior Design Engineer

Jul 2006 – Feb 2008 · 1 yr 7 mos

Here was working as a Senior Design for the Foundation IP group. I was working on Standard cell library development,characterization and QA of libraries. Technology nodes which i have worked on include 65nm , 90 , 130 and 150nm. I was also responsilble for release of libraries to various BUs.

International institute of information technology

Research/Teaching Assistant

Jun 2004 – Jun 2006 · 2 yrs

Here i was working as a Research and Teaching Assistant. My research focus was target on Low-power interconnect design. During my tenure i have developed low power coding algorithims for minimizing energy and delay on VLSI interconnects. I have published around 20 international during my research phase.