Viswanadh Karteek

Software Engineer

Bengaluru, Karnataka, India7 yrs 8 mos experience

Key Highlights

Expert in CPU verification and UVM methodologies.
Proficient in x86 and RISC-V architecture modeling.
Strong background in functional verification and test planning.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in CPU architecture and verification methodologies.

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Skills

Core Skills

Universal Verification Methodology (uvm)Python (programming Language)Functional VerificationCpu VerificationSystem Verilog

Other Skills

VerdiTestbenchAI toolsCoverageRISC-VLoad store block level verificationC++Core verif toolsx86RubyPerlDDR SDRAMDebugging

About

C++|Ruby|Perl|x86|RISC-V|Test planning|ASM|Automation|UVM|

Experience

7 yrs 8 mos

Total Experience

Average Tenure

Current Experience

Tenstorrent

3 roles

Staff Engineer

Apr 2026 – Present · 2 mos

Senior Engineer

May 2024 – Present · 2 yrs 1 mo

1: Verification of the Load/Store Unit.
2: Microarchitecture-level verification of Stores, including unit test planning, sequence development, and enabling UVM checkers/scoreboards.
3:Verification of various Load/Store microarchitecture features: Atomics, Cache Management Operations (CMOs), LR/SC, Memory FENCEs, and TLB invalidation.
4: Development of a unit-level UVM testbench.
5: Implementation of assertions.
6: Achieving end-to-end coverage.
7: Leveraging AI tools to enhance productivity.

Universal Verification Methodology (UVM)Python (Programming Language)VerdiTestbenchAI tools

Engineer

Jan 2023 – May 2024 · 1 yr 4 mos

CPU AI/ML Start-up

CoverageFunctional Verificationcpu verificationsystem verilogUniversal Verification Methodology (UVM)Python (Programming Language)+3

Amd

2 roles

Sr.Silicon Design Engineer

Jun 2022 – Jan 2023 · 7 mos · Bengaluru, Karnataka, India

x86 CPU Modelling (C++)
A software model for the X86 architecture.The X86 software model is used by processor and SOC verification teams as the primary means of determining the correctness of all AMD processor designs. The model can be coupled with a SystemVerilog coverage model to provide coverage of the x86 architecture. Responsible for adding new features to the x86 model and the coverage model and fixing bugs in both models.

cpu verificationsystem verilogCore verif toolsx86RubyC+++1