Sahit Babu P.

Software Engineer

Bengaluru, Karnataka, India15 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

12 years of experience in Physical Design Engineering.
Expert in Static Timing Analysis and Power Recovery.
Proficient in automation using TCL and Perl.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Automation.

Contact

Skills

Core Skills

Physical Design EngineeringStatic Timing AnalysisAutomationDigital DesignMicroarchitecture

Other Skills

P&RLVSDRCSTAIR analysisPower recoveryCTSTCLPerlCustom ImplementationArchitecture DesignALU DesignSRAM DesignDesign FlowFloor Plans

About

-> Physical Design Engineer with 12 years of experience in Auto Place and Route, STA, Power recovery, LVS and DRC, Dynamic IR drop analysis -> Automation using TCL, Shell, Perl. -> Good exposure on tools Encounter/Innovus, Primetime,Calibre.

Experience

15 yrs

Total Experience

5 yrs

Average Tenure

13 yrs 3 mos

Current Experience

Broadcom inc.

Principal Physical Design Engineer

Mar 2013 – Present · 13 yrs 3 mos · Bengaluru, Karnataka, India

Projects:-
1) Executed block level P&R which has 1.6M+ instances and 120 macros, 4 functional clocks and 208 debug clocks driving the functional debug logic.
Responsibilities:- Performed P&R, LVS, DRC, timing closure, STA checks and IR analysis
Challenges:- Two blocks merged to save area. Congestion, Functional debug logic with debug clocks. Understanding the clock structure and implementing CTS with less latency. Placement of debug logic.
2) Executed block level P&R for 500K+ instance, 32 macro block in 16nm, 2 functional clocks
Responsibilities:- Performed P&R, LVS, DRC, timing closure, STA checks and IR analysis
Challenges:- Memory Intense block; Congestion in memory channels, Timing closure on
Memory to register paths involving ECC logic, source synchronous interface and implementation of true random sequence generator.
3) Executed block level P&R which has 1M+ instances along with the embedded sub blocks with instance count of 500K for a 28nm backplane line card ASICs whose clock structure has multiplexers.
Responsibilities:- Performed P&R, LVS, DRC, timing closure, STA checks and IR analysis
Challenges:- Balancing clocks to embedded sub blocks and Timing closure in various modes,
Power recovery, Multiplexing clocks
4) Executed block level P&R for a 1.5M instance, 105 macro block along with embedded ARM9 processor in 28nm, 4 functional clocks
Responsibilities:- Performed P&R, LVS, DRC, timing closure, STA checks and IR analysis
Challenges:- Congestion and clock arrival times to all the ARM processors to be equal
Cross clock path timing closure, Power recovery.

P&RLVSDRCSTAIR analysisPower recovery+3

Cypress semiconductor corporation

Design Engineer

Jun 2012 – Mar 2013 · 9 mos · Bangalore

[1] Worked on Netlist-GDSII for 300K isntance, 25 macro and 500K instance 10 macro blocks, tasks involving P&R, LVS, DRC.
[2] Involved in automation of tasks using TCL/Perl.

P&RLVSDRCTCLPerlPhysical Design Engineering+1

Intel

Graduate Intern Technical

May 2011 – May 2012 · 1 yr · Bangalore,India

> Worked on Custom Implementation of blocks for Intel Processor Core
[1] 1) Involved in implementing new architecture for Fused Multiply-Add unit (axb+c),to validate the claims of performance improvement.
2) As a part the of project, worked on the Parallel-Prefix adder(Ladner Fischer) and Logarithmic shifters and integrating all of the hardmacros.
[2] 1) Design a simple 8 bit ALU with a 8 logarithmic adder , 8 bit AND,OR,EXOR and 8 bit Logarithmic
shifter
2) Design a 64 x 8 SRAM using standard SRAM cells and address decoders.

Custom ImplementationArchitecture DesignALU DesignSRAM DesignDigital DesignMicroarchitecture