P

Prafull Bhalerao

CEO

Bengaluru, Karnataka, India21 yrs 3 mos experience

Key Highlights

  • Expert in low power design verification.
  • Extensive experience in ASIC and VLSI engineering.
  • Proven leadership in engineering management.
Stackforce AI infers this person is a Low Power Design Verification expert in the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

Low Power Design VerificationEngineering

Other Skills

ManagementSoCVLSISystemVerilogFunctional VerificationASICVerilogDebuggingFormal VerificationLow-power DesignLow Power SystemsTiming ClosureSystem on a Chip (SoC)

Experience

21 yrs 3 mos
Total Experience
--
Average Tenure
--
Current Experience

Google

Low Power Design Verification Lead

Jan 2023 – Present · 3 yrs 5 mos · Bengaluru, Karnataka, India · On-site

low power design verificationEngineeringManagement

Western digital

Technologist, ASIC Developement Engineering

Mar 2021 – Aug 2023 · 2 yrs 5 mos · Bangalore Urban district, Karnataka, India

Engineering

Qualcomm

3 roles

Staff Enginner

Oct 2016 – Mar 2021 · 4 yrs 5 mos · Bengaluru Area, India

Engineering

Staff Engineer

May 2015 – Jan 2016 · 8 mos

Engineering

Sr Lead Engineer

Sep 2012 – May 2015 · 2 yrs 8 mos

Engineering

Intel corporation

Component Design Engineer

Jan 2016 – Oct 2016 · 9 mos · Bengaluru Area, India

Engineering

Freescale semiconductor

2 roles

Lead Design Engineer

Promoted

Jan 2012 – Sep 2012 · 8 mos

Engineering

Senior Design Engineer

Dec 2006 – Dec 2011 · 5 yrs

Engineering

Nvidia graphics

Hardware Engineer

Aug 2005 – Nov 2006 · 1 yr 3 mos · Bengaluru Area, India

Engineering

Bharti airtel limited

Engineer

Jun 2002 – Jan 2003 · 7 mos

  • Network Managment Center, Bhopal
Engineering

Education

Indian Institute of Technology, Kharagpur

Master of Technology (M.Tech.) — Microelectronics and VLSI

Jan 2003 – Jan 2005

Shri G.S. Institute of Tech. & Science Indore

BE — Electronics & Telecom

Jan 1998 – Jan 2002

Bal Vinay Mandir

SSc

Jan 1986 – Jan 1997

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