Chandra Bihari Goyal — Software Engineer
Expertise: Strong knowledge in digital design and CMOS technology. • Strong knowledge on ASIC design flow • Good knowledge in STA concepts • Hands on experience in Cadence Place & Route design implementation. Like Floor planning, Power planning, Placement, Clock Tree Synthesis, Routing (fixing DRC’s). • Able to do PrimeTime reports analysis and ECO fixes. • Good exposure to technology by undergoing additional training in VLSI Guru. • Excellent knowledge of ASIC Design. • Good understanding of Linux commands. Worked on 28nm technology from netlist to GDSII at VLSI Guru Technologies. Exposure: Place & Route flow using Cadence Place and route tool FIRST ENCOUNTER • Floor planning & Power Planning • Placement • Clock tree synthesis • Routing • Timing closure • Physical Verification STA: Primetime, SYNOPSYS [Got this experience by reading SYNOPSYS user manuals from google] • PT Timing Reports analysis • Ability to prepare Timing ECO’s in primetime VLSI Design Tools: CADENCE: First Encounter SYNOPSYS: PrimeTime,ICC
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and VLSI technologies.
Location: Bengaluru, Karnataka, India
Experience: 9 yrs 3 mos
Skills
- Analog Design
- Layout Design
Career Highlights
- Expert in digital design and CMOS technology.
- Hands-on experience with Cadence Place & Route tools.
- Strong background in ASIC design and VLSI.
Work Experience
Intel Corporation
Silicon Engineer (4 yrs 8 mos)
Qualcomm
Senior Physical Design Engineer (2 yrs 7 mos)
L&T Technology Services Limited
Physical Design Engineer (2 yrs)
Caliber Embedded Technologies India P Ltd
RTL Design Engineer (3 mos)
Digicomm Semiconductor Private Limited
Analog Layout Trainee (5 mos)
Bharat heavy Electrical Ltd Jhansi
3D CNC MACHINE (3 mos)
Education
Master of Technology - MTech at Vellore Institute of Technology
Engineer’s Degree at Rajiv Gandhi Prodyogiki Vishwavidyalaya