Hardik Jirawala

Software Engineer

Bengaluru, Karnataka, India11 yrs 11 mos experience

Highly Stable

Key Highlights

Expert in Physical Design and VLSI methodologies.
Proven track record in SoC design for high-performance applications.
Strong collaboration skills with cross-functional teams.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and Physical Design.

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Skills

Core Skills

Physical DesignVlsiStatic Timing AnalysisSoc DesignClock Tree Synthesis

Other Skills

Teamworkfloor planningApplication-Specific Integrated Circuits (ASIC)Synopsys toolsDesign Rule Checking (DRC)Full Chip LayoutPlace and RoutePlace & RouteTiming ClosureIC LayoutSynopsys PrimetimeDigital ElectronicsTCLPerl

Experience

11 yrs 11 mos

Total Experience

5 yrs 7 mos

Average Tenure

10 mos

Current Experience

Cadence

Principle Design Engineer

Aug 2025 – Present · 10 mos · Bengaluru, Karnataka, India · On-site

Teamworkfloor planningApplication-Specific Integrated Circuits (ASIC)Clock Tree SynthesisSynopsys toolsDesign Rule Checking (DRC)+12

Arm

Staff Engineer

Feb 2023 – Sep 2025 · 2 yrs 7 mos

Intel corporation

3 roles

SoC Design Engineer

Mar 2019 – Feb 2023 · 3 yrs 11 mos

Working on Multiple graphics and server SoC design involving timing closure of partitions and Subsystems with >50M gates and >3Ghz frequency for MCMM scenarios.
Continuous collaboration with CLK/Design/DFX teams cover timing aspects and design features in different PV conditions and generating FC and block level timing constraints.

Static Timing AnalysisIC LayoutSoC Design

Physical Design Engineer

Jul 2015 – Mar 2019 · 3 yrs 8 mos

Owned complete design flow execution involving synthesis, floor-planning, placement, CTS, routing, and power optimization for multiple partitions with >5-10M gates and >2GHz frequency designs.
Lead and worked with 4-5 Junior team members on multiple FCL activities involving Global clock tree building, critical data bus routing and optimization using multiple NDRs and routing constraints, physical integration and DRC/LVS cleanup. Expertise in fixing routing congestion on FC floorplan and timing optimization by RC delay fixes.

Static Timing AnalysisClock Tree SynthesisPhysical Design