Sathish Pochampalli

Product Engineer

Hyderabad, Telangana, India3 yrs 11 mos experience

Most Likely To Switch

Key Highlights

Published and granted 4 patents in ASIC design.
Expertise in synthesis and static timing analysis.
Experience with leading tools like Fusion Compiler and PrimeTime.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC design and embedded systems.

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Skills

Core Skills

SynthesisStatic Timing AnalysisPhysical DesignEmbedded Systems

Other Skills

Design Rule Checking (DRC)Logical, physical aware synthesisPower planningTCLTCSHDC_shellICC2_shellEmbedded Software ProgrammingElectrical EngineeringLECConformal LECCongestion analysisClock Tree SynthesisPlace & RouteTiming Closure

About

Presently working as Synthesis and STA Engineer . Have experience in Physical design as well. I have knowledge on ASIC Design, synthesis,STA ,PD . -> I worked on Fusion Compiler, DC ,Genus for Synthesis. Formality , Conformal For LEC . Worked on Timevison and PrimeTime for SDC checks. Performed QC checks ERC, CLP, LEC, TV-SDC, CtsSanity . -> I have PG diploma certification from JainX University on ASIC Design. Graduated from OSMANIA UNIVERSITY in First Class. ->I Published and Granted 4 patent rights from Intellectual Property India 🇮🇳

Experience

3 yrs 11 mos

Total Experience

1 yr 3 mos

Average Tenure

2 yrs

Current Experience

Qualcomm

Design Implementation Engineer

Jun 2024 – Present · 2 yrs · Bengaluru, Karnataka, India

Mediatek

Synthesis & STA Engineer

Nov 2022 – Jun 2024 · 1 yr 7 mos · Bengaluru, Karnataka, India · On-site

Design Rule Checking (DRC)Logical, physical aware synthesisSynthesisStatic Timing Analysis

Sumedhait

Physical design trainee

May 2022 – Nov 2022 · 6 mos · Hyderabad, Telangana, India

Trained on VLSI Physical design. I have gained knowledge on STA , SYNTHESIS, PNR. Im proficient in TCL and TCSH. I have worked on DC_shell & ICC2_shell.

Design Rule Checking (DRC)Power planningTCLTCSHDC_shellICC2_shell+2